基于宏细胞池的基数2蝴蝶的WSI设计

Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI) Pub Date : 1994-01-19 DOI:10.1109/ICWSI.1994.291239

T. K. Callaway, E. Swartzlander

{"title":"基于宏细胞池的基数2蝴蝶的WSI设计","authors":"T. K. Callaway, E. Swartzlander","doi":"10.1109/ICWSI.1994.291239","DOIUrl":null,"url":null,"abstract":"The use of a design strategy employing a hierarchy of structures, each with its own fault circumvention strategy can greatly improve the yield of WSI. At the circuit level, the strategy used is macrocell pooled redundancy. There are two basic types of macrocell pooled redundancy: 1 from N, and M from N. These two strategies are applied to the design of a radix 2 butterfly circuit for an FFT processor, and the effects of the choice of pooling strategy upon the yield are shown.<<ETX>>","PeriodicalId":183733,"journal":{"name":"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"WSI design of a radix 2 butterfly using macrocell pools\",\"authors\":\"T. K. Callaway, E. Swartzlander\",\"doi\":\"10.1109/ICWSI.1994.291239\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The use of a design strategy employing a hierarchy of structures, each with its own fault circumvention strategy can greatly improve the yield of WSI. At the circuit level, the strategy used is macrocell pooled redundancy. There are two basic types of macrocell pooled redundancy: 1 from N, and M from N. These two strategies are applied to the design of a radix 2 butterfly circuit for an FFT processor, and the effects of the choice of pooling strategy upon the yield are shown.<<ETX>>\",\"PeriodicalId\":183733,\"journal\":{\"name\":\"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)\",\"volume\":\"68 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-01-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICWSI.1994.291239\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICWSI.1994.291239","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

采用采用层次结构的设计策略，每个结构都有自己的故障规避策略，可以大大提高WSI的产量。在电路级，使用的策略是macrocell池冗余。有两种基本类型的宏细胞池冗余:1来自N和M来自N。这两种策略应用于FFT处理器的基数2蝴蝶电路的设计，并显示了池化策略的选择对良率的影响。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

WSI design of a radix 2 butterfly using macrocell pools

The use of a design strategy employing a hierarchy of structures, each with its own fault circumvention strategy can greatly improve the yield of WSI. At the circuit level, the strategy used is macrocell pooled redundancy. There are two basic types of macrocell pooled redundancy: 1 from N, and M from N. These two strategies are applied to the design of a radix 2 butterfly circuit for an FFT processor, and the effects of the choice of pooling strategy upon the yield are shown.<>

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)

自引率

0.00%

发文量