混合wsi的最佳芯片尺寸

Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI) Pub Date : 1994-01-19 DOI:10.1109/ICWSI.1994.291231

P. Singh, D. Landis

{"title":"混合wsi的最佳芯片尺寸","authors":"P. Singh, D. Landis","doi":"10.1109/ICWSI.1994.291231","DOIUrl":null,"url":null,"abstract":"The inter-chip delay penalty for hybrid-WSI and MCM designs is much lower than that for printed wiring boards. Consequently, the system partitioning and die size optimization problems must be attacked using a different set of parameters. This paper develops a new figure of merit for optimal HWSI/MCM chip sizing based upon system quality level, cost, and silicon efficiency. The figure of merit is then applied to a 500k gate MCM case study.<<ETX>>","PeriodicalId":183733,"journal":{"name":"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Optimal chip sizing for hybrid-WSI\",\"authors\":\"P. Singh, D. Landis\",\"doi\":\"10.1109/ICWSI.1994.291231\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The inter-chip delay penalty for hybrid-WSI and MCM designs is much lower than that for printed wiring boards. Consequently, the system partitioning and die size optimization problems must be attacked using a different set of parameters. This paper develops a new figure of merit for optimal HWSI/MCM chip sizing based upon system quality level, cost, and silicon efficiency. The figure of merit is then applied to a 500k gate MCM case study.<<ETX>>\",\"PeriodicalId\":183733,\"journal\":{\"name\":\"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-01-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICWSI.1994.291231\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICWSI.1994.291231","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

混合wsi和MCM设计的芯片间延迟惩罚远低于印刷布线板。因此，必须使用一组不同的参数来解决系统分区和芯片尺寸优化问题。基于系统质量水平、成本和硅效率，提出了一种优化HWSI/MCM芯片尺寸的新优值。然后将优点值应用于500k栅极MCM案例研究。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Optimal chip sizing for hybrid-WSI

The inter-chip delay penalty for hybrid-WSI and MCM designs is much lower than that for printed wiring boards. Consequently, the system partitioning and die size optimization problems must be attacked using a different set of parameters. This paper develops a new figure of merit for optimal HWSI/MCM chip sizing based upon system quality level, cost, and silicon efficiency. The figure of merit is then applied to a 500k gate MCM case study.<>

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)

自引率

0.00%

发文量