Optimal chip sizing for hybrid-WSI

Abstract

The inter-chip delay penalty for hybrid-WSI and MCM designs is much lower than that for printed wiring boards. Consequently, the system partitioning and die size optimization problems must be attacked using a different set of parameters. This paper develops a new figure of merit for optimal HWSI/MCM chip sizing based upon system quality level, cost, and silicon efficiency. The figure of merit is then applied to a 500k gate MCM case study.<>