Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI最新文献

{"title":"An overview of thermal management for next generation microelectronic devices","authors":"S. S. Tonapi, R. Fillion, F.J. Schattenmann, H.S. Cole, J. D. Evans, B. Sammakia","doi":"10.1109/ASMC.2003.1194502","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194502","url":null,"abstract":"The need for smaller, faster and lighter products has put considerable demands on the thermal management of microelectronics. This paper outlines the issues in thermal management of consumer and aerospace electronics. Some typical solutions for complex high-end systems are presented. The role of the thermal interface material is a key to the thermal management of high performance consumer electronics and is also addressed in this paper.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115388934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electrical properties of MOCVD HfO/sub 2/ dielectric layers with polysilicon gate electrodes for CMOS applications","authors":"L. Date, Z. Rittersma, D. Massoubre, Y. Ponomarev, F. Roozeboom, D. Pique, L. van-Autryve, S. Van Elshocht, M. Caymax","doi":"10.1109/ASMC.2003.1194482","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194482","url":null,"abstract":"Electrical properties of MOS capacitors using MOCVD HfO/sub 2/ as gate dielectric have been investigated. A 900/spl deg/C 1s activation anneal of Ph-doped 680/spl deg/C-RTCVD demonstrated a good compatibility with high-k layers. The best MOS capacitor is obtained with EOT=1.93 nm and Jg = 1.6E-04 A/cm/sup 2/ at |V/sub FB/-1| which is > 2 orders of magnitude lower than SiO/sub 2/ with poly-Si gate. A minimal degradation of leakage current after 900/spl deg/C activation anneal and low effect of temperature dependence reveal the thermal stability of MOCVD HfO/sub 2/ gate stack. Nevertheless, upon 1000/spl deg/C activation anneal only the LPCVD poly resulted in working MOS capacitor. The found leakage current was > 2 order of magnitude higher compared to a 900/spl deg/C activation anneal.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116998319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Wafer backside inspection applications in lithography","authors":"K. Lederer, M. Scholze, U. Strohbach, A. Wocko, T. Reuter, A. Schoenauer","doi":"10.1109/ASMC.2003.1194459","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194459","url":null,"abstract":"As the Semiconductor Industry starts to ramp its 110 nm production capacity, the need for optimal uniformity across the wafer surface becomes a very important topic in lithography. Due to the tightening of depth of focus requirements, the process window required to be able to print the required structure leaves little or no room for any localized deviation in the wafer uniformity. For 300 mm semiconductor device manufacturing, this resulted in the use of double-side polished, so-called \"super flat\", wafers. This paper discusses methods to identify yield relevant defects on the wafer backside without having to sacrifice wafers. It is based on recent studies carried out at both Infineon Semiconductor 200 and 300 mm Fabs in Dresden to characterize the need and the effectiveness of wafer backside defect inspection using the BSIM (Back Side Inspection Module) on the Surfscan/sup /spl reg// SP1/sup TB1/. Firstly, we focus on some general topics of setting up a backside inspection for photolithography. We show how to determine the required sensitivity in order to capture the defects of interest and to provide quantitative information on the number of wafers affected. We then discuss two studies in detail: The 1st study was an investigation into the quality of the backside of 300 mm wafers pre and post lithography throughout the manufacturing process. The 2nd study describes how focus spots on the front side of 200 mm wafer were correlated to damage on the backside and how the root cause was identified. Finally, we draw an outline to requirements that we believe will be an essential part of automatic backside inspection in the forthcoming future.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127012121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Advanced analysis of dynamic neural control advisories for process optimization and parts maintenance","authors":"J. Card, W. Chan, A. Cao, W. Martin, J. Morgan","doi":"10.1109/ASMC.2003.1194514","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194514","url":null,"abstract":"This paper details an advanced set of analyses designed to drive specific process variable setpoint adjustments or maintenance actions required for cost effective process control using the Dynamic Neural Controller/spl trade/ (DNC) wafer-to-wafer advisories for semiconductor manufacturing advanced process control. The new analytic displays and metrics are illustrated using data obtained on a LAM 4520XL at STMicroelectronics as part of a SEMATECH SPIT beta test evaluation. The DNC represents a comprehensive modeling environment that uses as its input extensive process chamber information and history of the time since maintenance actions occurred. The DNC uses a neural network to predict multiple quality output metrics and a closed-loop risk-based optimization to maximize process quality performance while minimizing overall cost of tool operation and machine downtime. The software responds in an advisory mode on a wafer-to-wafer basis as to the optimal actions to be taken. In this paper, we present three specific instances of patterns arising during wafer processing over time that signal the process or equipment engineer to the need for corrective action: either a process setpoint adjustment or specific maintenance actions. Based on the controller's recommended corrective action set with the overall risk reduction predicted by such actions, a metric of corrective action \"urgency\" can be created. The tracking of this metric over time yields different pattern types that signify a quantified need for a specific type of corrective action. Three basic urgency patterns are found: 1. a pattern in a given maintenance action over time showing increasing urgency or \"risk reduction\" capability for the action; 2. a pattern in a process variable specific to a given recipe indicating a chronic request over time to only adjust the variable setpoint either above or below the current target; 3. a pattern in a process variable existing over all recipes processed through the chamber indicating chronic request to adjust the variable setpoint in either or both directions over time. This pattern is a pointer to the need for a maintenance action that is either corroborated by the urgency graph for that maintenance action, or if no such action has been previously taken, a guide to the source of the equipment malfunction.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121720122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Dopant redistribution and loss during ternary silicide Co/sub x/Ni/sub 1-x/Si/sub 2/ formation","authors":"Y.Q. Xu, J. Zhao, J.P. Lu, D. Miles, J. Loewecke, P. Tiner, Xia Dong, S. Novak","doi":"10.1109/ASMC.2003.1194489","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194489","url":null,"abstract":"As CMOS devices are scaled to sub-100 nm region, dopant loss during silicide anneal becomes a critical issue. Reducing the thermal budget for silicide anneal is desirable to minimize the dopant loss from source/drain and polysilicon gate. With ternary silicide Co/sub x/Ni/sub 1-x/Si/sub 2/, a relatively low anneal temperature can be used to achieve the disilicide phase with a comparable resistance value to CoSi/sub 2/. In this report, the sheet resistance of Co/sub x/N/sub 1-x/Si/sub 2/ (x=1-0.5) at different anneal temperatures has been studied. The dopant redistribution and loss during Co/sub x/Ni/sub 1-x/Si/sub 2/ formation were characterized by secondary ion mass spectrometry (SIMS). In addition, the phase structures of Co/sub x/Ni/sub 1-x/Si/sub 2/ formed were also compared by X-ray diffraction (XRD). The results indicate that an optimal silicide process with low thermal budget can be achieved in ternary silicide Co/sub x/Ni/sub 1-x/Si/sub 2/ structures to reduce dopant loss at source/drain junctions and poly gate, while keeping silicide resistance low.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131358741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Alignment and overlay metrology using a spectroscopic diffraction method","authors":"Weidong Yang, R. Lowe-Webb, J. Heaton, M. Dusa, M. van der Schaar","doi":"10.1109/ASMC.2003.1194465","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194465","url":null,"abstract":"As lithographic technology drives the integrated-circuit feature size towards 0.1 micron and below, overlay and alignment tolerances are becoming increasingly severe. State-of-the-art aerial imaging overlay metrology systems are limited in accuracy due to inherent limitation on tool imaging resolution and aberrations inherent to the optical system. These in effect result in measurement inaccuracy exceeding industry requirements for next generation overlay tolerances. In this paper, a spectroscopic, diffraction based, technique is proposed as an alternative solution for overlay metrology and alignment measurement in sub 0.1 micron node. With one diffraction grating on the surface overlaying a second diffraction grating on a reference layer, the spectroscopic reflection is modulated by the relative position of the two gratings. Thus, the alignment error can be extracted from broadband diffraction efficiency of measurement pads constituent to the alignment target. This novel diffraction-based overlay metrology has inherent advantages over the traditional image-based overlay metrology: the targets are less sensitive to process variations, and spectroscopic diffraction measurements are less affected by the inherent aberration of the optical system. For these reasons, a diffraction-based spectroscopic metrology has higher potential to generate overlay data that is directly related to registration errors due to alignment and not due to the process or tool aberrations. As a consequence, this technology has a higher potential to generate accurate data to correct registration errors during the lithographic process. Feasibility and accuracy of the technique is studied through a set of experiments and of rigorous simulations on grating targets with various line-width and line-to-space ratios. Correlation to aerial imaging overlay measurements is demonstrated. The results suggest the technique is capable of achieving or exceeding overlay and alignment control accuracy requirements for sub 0.1 micron design rules.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"276 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124445586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Laser shock cleaning of inorganic micro and nanoscale particles","authors":"A. Busnaina, J. Park, J. Lee, S. You","doi":"10.1109/ASMC.2003.1194464","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194464","url":null,"abstract":"A new dry cleaning technology: laser-induced shock cleaning has been applied to remove the submicron particles (including post-CMP (chemical-mechanical polishing)) slurries from silicon wafer surfaces. The cleaning effectiveness of the new technology was evaluated quantitatively using a laser surface scanner. The results show that most of the silica particles on the wafer surface were removed after exposure to the laser-induced shock waves. The average removal efficiency of the particles was over 99%. The results show that cleaning efficiency is strongly dependent on a gap distance between laser focus point and the wafer surface and that a suitable control of the gap is crucial for the successful removal of the particles. In addition, this new technique was also applied successfully to the removal of the post-CMP slurries from polished patterned wafers.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114614208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A pragmatic approach to managing APC FDC in high volume logic production","authors":"R. Joyce-Wohrmann","doi":"10.1109/ASMC.2003.1194511","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194511","url":null,"abstract":"At Infineon Technologies APC fault detection is now implemented in many process areas in its high volume fabs. With the APC Software \"APC-Trend\" process engineers and maintenance can detect and classify anomalies in machine and process parameters and supervise them on the basis of an automated alarming system. An overview of the current usage of APC FDC at Infineon is given.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114911697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A scheduling and resource optimising MES for the semiconductor and MEMS industry","authors":"J. Sieberg, R. Walter","doi":"10.1109/ASMC.2003.1194476","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194476","url":null,"abstract":"While the number of custom specific products is increasing, the order size often diminishes. This problem leads to difficulties in managing demand changes, promising accurate dates and ensuring optimal equipment utilization. A real-time information gap exists in the heart of most manufacturing enterprises, since there is a lack of visibility and predictability. The scheduling of manufacturing orders bears great optimization potential. Based on modern MES with maximum equipment integration, the use of automatic process control and optimization enables SME to be more competitive, efficient and customer-friendly.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116200853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Precision and accuracy of CD-SEM profile reconstruction for the 110 technology node","authors":"T. Marschner, C. Stief","doi":"10.1109/ASMC.2003.1194467","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194467","url":null,"abstract":"We use CD-SEM side-wall imaging on the Applied Materials NanoSEM 3D system as a destruction free and quick method to determine side-wall profiles. From two different tilt angles up to 15 degrees the reconstruction of side-wall profiles is possible in a quick and non destructive way even for negatively sloped profiles. We demonstrate precision and accuracy of height and side-wall angle determination on selected examples. Additionally we demonstrate the fully automatic determination of the spatial frequency of LER on samples containing artificial LER of different amplitudes and spatial frequencies. Finally, we use the beam tilt capability SEM to investigate 193 nm resist line edge roughness (LER) and the transfer of this LER into etch. We show how top and bottom LER can be separated from each other by measuring the same sample at different beam tilt angles. The demonstrated methods reduce cycle time significantly and saves wafers for time consuming X-SEM investigations.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126822467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}