R. Sonnemans, C. Waldfried, A. Rastegar, M. Broekaart
{"title":"Process advances in plasma photoresist and residue removal with the use of H/sub 2/O vapor","authors":"R. Sonnemans, C. Waldfried, A. Rastegar, M. Broekaart","doi":"10.1109/ASMC.2003.1194463","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194463","url":null,"abstract":"The benefits of H/sub 2/O-vapor, when added to a downstream plasma for post-via etch residue removal is discussed. This paper provides results of the polymer removal effectiveness of a FOx low-k post-via-etch application when H/sub 2/O vapor is added to the clean process plasma. Two significant findings are presented: (1) The importance of maintaining a low temperature during the residue removal step in order to prevent the 'hardening' of the residues, and (2) the benefit of using an intermediate plasma-free step that includes H/sub 2/O-vapor, for effective removal. Polymers were observed to separate from the sidewall during processes with the intermediate H/sub 2/O vapor step and rendered removable in a subsequent DI water rinse. This resulted in a significant enhancement of the yield, compared to the standard high temperature H/sub 2/O-vapor-free process of record.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116726583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An effective methodology for improving equipment reliability and reducing excursions during a factory ramp","authors":"S. Lantz","doi":"10.1109/ASMC.2003.1194510","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194510","url":null,"abstract":"This paper describes the continuous improvement methodology that was developed and used in the Cu CMP area of Intel's Fab 20 during the 0.13 /spl mu/m logic technology production ramp from July 2001 through Sept. 2002. Significant and lasting improvements were realized by the systematic application of manufacturing engineering principles. Although many technical process changes were made as a result of these activities, the main focus of the paper is the methodology employed and a reflection on the effectiveness of the key elements of overall effort.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124722527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Guided analytic application for interactive flash memory Vt and I-V classification using Spotfire DecisionSite","authors":"S. Shetty, C. Hopper","doi":"10.1109/ASMC.2003.1194495","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194495","url":null,"abstract":"This paper describes techniques to classify I-V curves and analyze resulting Vt distributions using interactive analytical tools developed and deployed for that purpose on a guided analytics platform called DecisionSite, from Spotfire Inc. An interaction between transistor performance and physical layout was characterized using these methods, and layout changes implemented to reduce this effect have significantly increased the level and consistency of device yield for a new flash memory product. The method for analysis has been encapsulated in a process guide, which facilitates sharing this best practice method with other engineering personnel through a centralized DecisionSite server.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126409323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Influence of defect capture rate on defect-yield-correlations and generally defect control strategies","authors":"T. Tochtrop","doi":"10.1109/ASMC.2003.1194461","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194461","url":null,"abstract":"The influence of defect capture rate on defect line control and defect-yield-correlations is discussed. Practical examples reveal, that even for \"biggest killing defects\" capture rates are far below 100%. An overview about associated defect line control problems is given. A simple model, taking recipe parameters such like gain and threshold into account is discussed to describe one origin. Three examples are given which prove the strong influence of capture rate variations on practical aspects of defectivity. This realization enforces to revise defect line control strategies and defect-yield-correlation models.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133663850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Simulation-based evaluation of the ramp-up behavior of waferfabs","authors":"R. Sturm, J. Dorner, K. Reddig, J. Seidelmann","doi":"10.1109/ASMC.2003.1194478","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194478","url":null,"abstract":"In this paper we present a simulation study of wafer fab ramp-up scenarios with the simulation software AutoSched AP. A generic factory model (MIMAC 1 from Int. SEMATECH) was adapted to simulate fab ramp-up scenarios. The model was customized to consider time phased modeling capability and time phased reporting. Additionally, an evaluation approach for the comparison of different ramp-up simulation scenarios is presented. This approach helps to evaluate the ramp-up performance with different input parameters. A systematic variation of dispatch rules and lot sizes during ramp-up is shown.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121786206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Horng, S. Lin, M.H. Cheng, F. Yang, C.H. Liu, W. Lee, C. Tsai
{"title":"Reducing the overkills and retests in wafer testing process","authors":"S. Horng, S. Lin, M.H. Cheng, F. Yang, C.H. Liu, W. Lee, C. Tsai","doi":"10.1109/ASMC.2003.1194508","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194508","url":null,"abstract":"Reducing overkills is one of the main objectives in the wafer testing process, however the major mean to prevent overkills is retest. In this paper, we formulate the problem of reducing overkills and retests as a stochastic optimization problem to determine optimal threshold values concerning the number of good dies and the number of bins in a lot and wafer to decide whether to go for a retest after a regular wafer probing. The considered stochastic optimization problem is an NP hard problem. We propose an Ordinal Optimization theory based two-level method to solve the problem for good enough threshold values to achieve lesser overkills and retests within a reasonable computational time. Applying to a case based on the true mean of bins of a real semiconductor product, the threshold values we obtained are the best among 1000 sets of randomly generated threshold values in the sense of lesser overkills under a tolerable retest rate.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123298387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. El-Sayed, S. Collins, D. Frystak, L. Loewenstein
{"title":"Cobalt silicide re-deposition during batch spray strip process resulting in open contacts","authors":"A. El-Sayed, S. Collins, D. Frystak, L. Loewenstein","doi":"10.1109/ASMC.2003.1194485","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194485","url":null,"abstract":"Functional fails due to open contacts were determined to be the main cause of systematic yield loss. Electrical analysis correlated the yield loss to single bit fails (SBIT) in the SRAM cell. Physical analysis on several SBIT fails showed blocked contacts due to titanium (Ti) defects in the silicide loop. Several partition experiments in the silicide loop pointed to the batch spray strip process as the main contributor to Ti defects. This paper describes the methodology used to isolate the open contacts to defects in the cobalt silicide (CoSi) loop starting at Co sputter and ending with Co anneal. It identifies the sources of Ti defects and determines the role of the batch spray strip process in forming these defects and blocking the contacts. Corrective actions put in place to reduce Ti, including the elimination of bare Si surfaces from the spray processor during Co strip.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133434586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Implementing fiducial probe card alignment technology for production wafer probing","authors":"D. Langlois, M. Fardel, K.R. Heiman, F. Du","doi":"10.1109/ASMC.2003.1194499","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194499","url":null,"abstract":"To match the ever-increasing density and performance of integrated circuits, new generations of probe cards are getting adopted in the main stream manufacturing process in a rapid pace. To match the product geometry and performance, probe tips are getting increasingly denser, product refined, and miniaturized. The appearances of these tips vary significantly between different technologies, wear and tear of the card, and even the cleaning technology used. To support the increasingly thorough testing process and fast product cycle, probers have to align the probe card automatically, reliably, quickly, and accurately. This poses great challenges to current technology. It takes a significant amount of time and effort for a prober to support new types of probe cards. To address this issue and issues related to test cell management and interoperability of probe card on different probers, we propose a new probe card support process centered on fiducials. Unlike individual probe tips, fiducials are probe card technology neutral and does not change appearances due to wear and tear. They provide reliable and accurate landmarks across different platforms. The proposed technology supports and enhances efficient communication between probe card manufacturers, prober manufacturers, and wafer manufactures. It provides effective means for semiconductor manufacturers to automate probe card setup, tracking, management, and utilization.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133139336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Optimization of automated material handling systems regarding robustness and delivery time","authors":"D. Gluer","doi":"10.1109/ASMC.2003.1194475","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194475","url":null,"abstract":"Automated Material Handling Systems (AMHS) are becoming more and more essential for economical working Megafabs. Managing large numbers of Work in Process (WIP) requires advanced logistical support strategies such that lots arrive Just In Time at their destination, to minimize cycle time. This makes robust AMHS design mandatory with short delivery times, at least from the operators perspective. In order to compare system and layout alternatives, appropriate metrics need to get defined, measured and compared. Traditionally, those alternatives are evaluated with discrete event simulations. But it remains cumbersome to determine certain parameters like the overall availability. A new approach will be presented to address this issue. The methods described above have been applied to AMD's Fab 30, and the results are briefly discussed.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129201146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Weidner, U. Mantz, P.Y. Guittet, R. Wienhold, M. Rimane, J. Stehle, P. Boher, M. Bucchia
{"title":"Introduction of infrared spectroscopic ellipsometry in a semiconductor production environment","authors":"P. Weidner, U. Mantz, P.Y. Guittet, R. Wienhold, M. Rimane, J. Stehle, P. Boher, M. Bucchia","doi":"10.1109/ASMC.2003.1194501","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194501","url":null,"abstract":"IRSE proposes a complementary type of characterization to widely accepted UV-VIS ellipsometry. IRSE is sensitive to absorption bands (vibrational and rotational states of molecules) and free carriers. IRSE reduces also sensitivity to scattering due to roughness or very small CDs. We present here an IRSE production tool integrated in clean-room class 1: the SOPRA IRSE200. Our first objective is to assess IRSE capabilities for better sensitivity, stability and throughput for thin epilayers (20 nm-120 nm) thickness monitoring. A production strategy is developed on this topic.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123394464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}