Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI最新文献

{"title":"Effect of PECVD SiC and SiCN cap layer deposition on mesoporous silica ultra low k dielectric films","authors":"S. Schulz, K. Schulze, J. Matusche, U. Schmidt, T. Gessner","doi":"10.1109/ASMC.2003.1194481","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194481","url":null,"abstract":"It is crucial to apply cap layers with minimum permittivity to ensure a minimum effective k-value of the whole dielectric stack. Therefore, the influence of the deposition of PECVD SiC and SiCN cap layers with k < 5.0 on the electrical and chemical properties of low k dielectric films is the subject of this work.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"65 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114016240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Continuously optimizing the value of an installed base of semiconductor manufacturing equipment","authors":"G. van der Feltz, F. Lamers, H. Priem, R. Melief","doi":"10.1109/ASMC.2003.1194513","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194513","url":null,"abstract":"As the semiconductor industry matures, equipment manufacturers need to change their focus on the way they approach their customers. In the more mature segments of the semiconductor equipment industry, technology is no longer the main industry driver. Instead, equipment manufacturers need to provide customized solutions that enable their customers to maximize the value of their installed base of wafer fab equipment for their specific situation. ASML started its Installed Base Solutions (IBS) program to better provide owners of mature equipment with the products and services they need. We are working with customers to get a better understanding of how their requirements change throughout both the lifecycle of the equipment as well as the market cycles of the semiconductor industry. This understanding of our customers' requirements led us to design and develop a portfolio of products and services that can be combined to produce solutions that help customers to continuously maximize the value generated by their installed base. This portfolio of products and services provides the elements needed to create complete solutions that extend beyond equipment and operational services. The products and services in the portfolio focus on the optimal use of lithography equipment in actual production processes. To achieve such solutions, a close relationship with the participating equipment users is essential. Results obtained using this approach - focussing on the optimal use of lithography equipment in actual production processes - indicate that we can generate significant additional value potential in all of the fabs that we considered.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124910950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact of additional LDD rapid thermal annealing on submicron n-MOSFETs","authors":"Qian Wensheng, V. Leong, Wang Yuwen, Li Yisuo, Pandey Shesh Mani, S. Manju, F. Benistant, S. Chu","doi":"10.1109/ASMC.2003.1194498","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194498","url":null,"abstract":"An additional NLDD Rapid Thermal Annealing (RTA) had been implemented in thin-gate and thick-gate NMOS transistors. The threshold voltage (Vt) distribution at different gate lengths was investigated for devices with and without NLDD RTA. Lower roll-up and roll-off of Vt was observed with the inclusion of NLDD RTA. However, this observation only occurred for phosphorus-LDD NMOS devices rather than arsenic-LDD NMOS devices. Based on experimental results, TCAD tools was applied to analyze the removal of implant-induced damages by LDD RTA and to investigate the difference in channel profiles before and after LDD RTA. Finally, the mechanism of less Reverse Short Channel Effect and Short Channel Effect with LDD RTA was presented through TCAD simulation results.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127934392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Airborne molecular contamination: On-line analytical system for real time contamination control","authors":"F. Illuzzi, P. Sonego, C. Landoni, C. Solcia, M. Succi, T. Bacon, K. Webber","doi":"10.1109/ASMC.2003.1194487","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194487","url":null,"abstract":"The attention of the IC makers for AMC contamination is gaining interest, in particular for its determination with real time techniques. For this purpose a dedicated system has been developed and tested. It allows determining total amines, total acids and multiple specific organic compounds. The data obtained during the test have shown that the concentration of impurities can often be related to production or maintenance processes and that their presence is characteristic for each area. Particular attention must also be paid to monitoring the filter efficiency.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127924124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Efficient lot batching system for furnace operation","authors":"K. Ibrahim, M. A. Chik, W.S. Nizam, N.L. Fern, N.F. Za'bah","doi":"10.1109/ASMC.2003.1194515","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194515","url":null,"abstract":"At a semiconductor foundry where a wide range of products are manufactured using the make-to-order model, it is important to optimize the lot batching in diffusion area since the loading size in most machines are in quantities of 100 to 150 wafers. This paper describes a real time dispatching system that has been developed to reduce lot queue time in the furnace operations. Emphasis on customer delivery date, bottleneck tool and batching behavior was given in rule building for the overall systems implementation in diffusion furnace operation. The main component of this project is the rule built considering queue time restriction between pre-clean and furnace operation, allowable waiting time to maximize the batch, queue time consideration to next process such as polysilicon deposition, furnaces due for scheduled maintenance, bottleneck tool idling, process cycle time versus lot priority considerations and etc. With the implementation of this system we are able to reduce manufacturing cost, increase tool utilization, reduce overall cycle-time and meet customer delivery dates. This implementation has resulted in much better material movement and has also made the manufacturing line more linear.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133757340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A semiconductor valid device development and production control methodology","authors":"S. Leibiger","doi":"10.1109/ASMC.2003.1194507","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194507","url":null,"abstract":"This paper presents a systematic approach for request, design, development, and production control of valid electronic devices for a semiconductor process technology. The principal objective is guaranteed equivalence of device silicon characteristics, electrical technology table specifications, and circuit simulation tools. This procedure also ensures that all device components are completed and delivered in a coordinated and effective manner to their various customers. Thus, both rapid design and effective production ramp and control can be achieved.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"15 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114028847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Productivity enhancement using a methodical approach to defect reduction based on synergy of process and defect metrology knowledge","authors":"R. Schreutelkamp, M. van der Reijden, T. King, K. Mast, I. Englard, J. Zondag, F. Rommel, S. Harzenetter, H. Schoel, J. Cavelaars, M. Swaanen, Liang Shi, H. Sahr, M. Gerwig, M. Junker, R. Poschadel, B. Hein","doi":"10.1109/ASMC.2003.1194460","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194460","url":null,"abstract":"Increased process equipment complexity and cost related to tool down time stimulate a stronger partnership between chip manufacturer and process equipment vendor to minimize the risk to production. Applied Materials is engaged in various process equipment-related service programs at customer manufacturing sites ranging from complementation of the manufacturer's own factory service organization to full ownership of equipment. In this paper, we discuss one aspect of service offerings that targets at defect reduction and productivity enhancement. Successful implementation at Philips Semiconductors of a methodology to perform defect reduction and productivity enhancement programs is discussed. Examples of using the described methodology are provided in this paper for programs targeted at DO baseline defect density reduction, mean wafer between clean (MWBC) improvement, and limitation of yield loss related to intermittent particle bursts.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122136000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Cost of yield","authors":"D. Maynard, D. Kerr, C. Whiteside","doi":"10.1109/ASMC.2003.1194488","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194488","url":null,"abstract":"Every semiconductor manufacturer carefully manages fixed and variable costs to achieve profitability. Usually this is well defined in terms of facilities, equipment, labor, and materials, and for the high volume single product producer, the story is complete. Allocating a factory's capacity across several or many products quickly complicates the picture, and the engineering staff is forced to prioritize issues across product subsets. Cost of yield (COY) is a measure of the additional dollars debited (credited) to production expenses when the aggregate productivity falls below (exceeds) the business plan. It provides a way to understand the economic impact of yield variation from the plan weighted by the costs and volumes of each product. COY has been calculated at IBM Microelectronics since 1995 when the division moved to a \"Standard Cost\" accounting system, and it continues to be an important business management tool. The management staff interprets COY data to validate resource allocations and insure the deployment of the correct activities that cover the products with the largest COY variances. In fact, COY can be subdivided by a number of dimensions, and the implications of these analysis reaches beyond the realm of accounting. A manufacturer develops the cost targets during its planning cycle by projecting productivities (and yield). Measuring COY validates and audits the planning process, and large COY variances trigger profit motivation questions. Moreover, the manufacturer can make an informed decision as to when to scrap degraded hardware. This paper discusses the mechanics of the COY calculation and illustrates the concepts with analysis examples. Suggested integration into and investigation by the manufacturing engineering community are shown. Gaining a true understanding of how specific decisions affect yield in terms of actual dollars forces the design community to be accountable for conscience yield-limiting decisions, and provides the right benefit measure of some design-for-manufacturing initiatives. Finally, the senior business decision makers can assemble an enterprise-level COY perspective to guide future investment and actions.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"2 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129435523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"New lithography excimer light source technology for ArF (193 nm) semiconductor manufacturing","authors":"D. Colon","doi":"10.1109/ASMC.2003.1194512","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194512","url":null,"abstract":"Future argon fluoride (ArF), 193 nm photolithography applications will require excimer light sources to generate very narrow spectral bandwidths at high output power. In order to meet these requirements, the traditional single-gas-discharge-chamber design used by lithography excimer light sources for the past ten years will transition to a new dual-chamber Master Oscillator Power Amplifier (MOPA) technology. MOPA will provide lithographers with significant performance benefits and manufacturing cost advantages at the 193 nm exposure wavelength. This paper will explain MOPA architecture and describe its numerous advantages vis-a-vis the single-chamber design.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126641513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Equipment engineering systems","authors":"E. Schobel","doi":"10.1109/ASMC.2003.1194492","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194492","url":null,"abstract":"The need of the semiconductor industry for fully automated production to reduce the production time and costs makes it necessary to control all equipment remotely. To make improvements possible it is necessary to have exact data of the current state of the production for each single equipment. Because the machines are connected already to the infrastructure the collection of data can be done also fully automated by using the equipment's information. Such a system is the TFM (Total Fab Monitoring) developed by AIS Automation GmbH. But with automating the daily work the risk is also increased if one of the systems in the architecture fails. Since the risk will ever be present the fabs need a solution to react on problems very fast. This was the reason for AIS to develop an e-diagnostic system VRC (VAC Remote Control). It is used productively in a modern fab in Dresden for supervising the equipment integration software and hardware which is the basis for the automation of the production. The paper describes these two important applications of the MES level.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133798154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}