L. Date, Z. Rittersma, D. Massoubre, Y. Ponomarev, F. Roozeboom, D. Pique, L. van-Autryve, S. Van Elshocht, M. Caymax
{"title":"用于CMOS应用的多晶硅栅电极MOCVD HfO/sub - 2/介电层的电学性能","authors":"L. Date, Z. Rittersma, D. Massoubre, Y. Ponomarev, F. Roozeboom, D. Pique, L. van-Autryve, S. Van Elshocht, M. Caymax","doi":"10.1109/ASMC.2003.1194482","DOIUrl":null,"url":null,"abstract":"Electrical properties of MOS capacitors using MOCVD HfO/sub 2/ as gate dielectric have been investigated. A 900/spl deg/C 1s activation anneal of Ph-doped 680/spl deg/C-RTCVD demonstrated a good compatibility with high-k layers. The best MOS capacitor is obtained with EOT=1.93 nm and Jg = 1.6E-04 A/cm/sup 2/ at |V/sub FB/-1| which is > 2 orders of magnitude lower than SiO/sub 2/ with poly-Si gate. A minimal degradation of leakage current after 900/spl deg/C activation anneal and low effect of temperature dependence reveal the thermal stability of MOCVD HfO/sub 2/ gate stack. Nevertheless, upon 1000/spl deg/C activation anneal only the LPCVD poly resulted in working MOS capacitor. The found leakage current was > 2 order of magnitude higher compared to a 900/spl deg/C activation anneal.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Electrical properties of MOCVD HfO/sub 2/ dielectric layers with polysilicon gate electrodes for CMOS applications\",\"authors\":\"L. Date, Z. Rittersma, D. Massoubre, Y. Ponomarev, F. Roozeboom, D. Pique, L. van-Autryve, S. Van Elshocht, M. Caymax\",\"doi\":\"10.1109/ASMC.2003.1194482\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Electrical properties of MOS capacitors using MOCVD HfO/sub 2/ as gate dielectric have been investigated. A 900/spl deg/C 1s activation anneal of Ph-doped 680/spl deg/C-RTCVD demonstrated a good compatibility with high-k layers. The best MOS capacitor is obtained with EOT=1.93 nm and Jg = 1.6E-04 A/cm/sup 2/ at |V/sub FB/-1| which is > 2 orders of magnitude lower than SiO/sub 2/ with poly-Si gate. A minimal degradation of leakage current after 900/spl deg/C activation anneal and low effect of temperature dependence reveal the thermal stability of MOCVD HfO/sub 2/ gate stack. Nevertheless, upon 1000/spl deg/C activation anneal only the LPCVD poly resulted in working MOS capacitor. The found leakage current was > 2 order of magnitude higher compared to a 900/spl deg/C activation anneal.\",\"PeriodicalId\":178755,\"journal\":{\"name\":\"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-04-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASMC.2003.1194482\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASMC.2003.1194482","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Electrical properties of MOCVD HfO/sub 2/ dielectric layers with polysilicon gate electrodes for CMOS applications
Electrical properties of MOS capacitors using MOCVD HfO/sub 2/ as gate dielectric have been investigated. A 900/spl deg/C 1s activation anneal of Ph-doped 680/spl deg/C-RTCVD demonstrated a good compatibility with high-k layers. The best MOS capacitor is obtained with EOT=1.93 nm and Jg = 1.6E-04 A/cm/sup 2/ at |V/sub FB/-1| which is > 2 orders of magnitude lower than SiO/sub 2/ with poly-Si gate. A minimal degradation of leakage current after 900/spl deg/C activation anneal and low effect of temperature dependence reveal the thermal stability of MOCVD HfO/sub 2/ gate stack. Nevertheless, upon 1000/spl deg/C activation anneal only the LPCVD poly resulted in working MOS capacitor. The found leakage current was > 2 order of magnitude higher compared to a 900/spl deg/C activation anneal.
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