2021 IEEE International Test Conference India (ITC India)最新文献

Accelerating GLS Simulation closure in DFT with Emulator 用仿真器加速DFT中的GLS仿真闭合

2021 IEEE International Test Conference India (ITC India) Pub Date : 2021-07-18 DOI: 10.1109/ITCIndia52672.2021.9532898

Kriti Sundar Das, P. Prakash, A. Zala

{"title":"Accelerating GLS Simulation closure in DFT with Emulator","authors":"Kriti Sundar Das, P. Prakash, A. Zala","doi":"10.1109/ITCIndia52672.2021.9532898","DOIUrl":"https://doi.org/10.1109/ITCIndia52672.2021.9532898","url":null,"abstract":"To keep pace with the demands of advanced complex SoC development and to close the HW /SW verification gap, Emulation is increasingly used as a scalable and reusable solution. As part of a quicker execution schedule, DFT Engineers deploy optimum methods of RTL, ATPG, MBIST verification, and even proto-type complete RTL into Emulator for faster RTL verification closure. Another integral part of DFT verification is Gate-Level Simulation of MBIST and ATPG patterns but done in small volume due to huge simulator-time requirement leading to incomplete closure. We propose vector-mode based Gate level emulation (GLE) for DFT patterns. This paper talks about 500-to-1500X performance gain when simulating MBIST and ATPG complete pattern set in Emulator over GLS. Results show that for 2 SOCs of size 36M, 55M gates, a complete stuck-at, and transition ATPG WGL format pattern set of 90k can be simulated in Emulator within hours. Manufacturing Algorithm-based MBIST WGL patterns which take weeks in the EDA simulator can be emulated in minutes. This provides closure of DFT Pre-silicon GLS Verification within a day. The verified WGL patterns can be seamlessly ported to ATE Tester program for post-silicon Bring-up, bridging the verification gap between RTL and silicon device. The paper also shows a method of debugging ATPG and MBIST pattern failures with debug logs and waveforms dumped from the Emulator program.","PeriodicalId":177825,"journal":{"name":"2021 IEEE International Test Conference India (ITC India)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122003037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Targeting Zero DPPM through Adoption of Advanced Fault Models and Unique Silicon Fall-out Analysis 通过采用先进的故障模型和独特的硅沉降分析，实现零DPPM

2021 IEEE International Test Conference India (ITC India) Pub Date : 2021-07-18 DOI: 10.1109/ITCIndia52672.2021.9532687

Aravind Acharya, Nikita Naresh, P. Narayanan, R. Parekhji, Kevin Roush, Humberto Ibarra, Rajiv Sheth, Clarence Flora, Wilson Pradeep

{"title":"Targeting Zero DPPM through Adoption of Advanced Fault Models and Unique Silicon Fall-out Analysis","authors":"Aravind Acharya, Nikita Naresh, P. Narayanan, R. Parekhji, Kevin Roush, Humberto Ibarra, Rajiv Sheth, Clarence Flora, Wilson Pradeep","doi":"10.1109/ITCIndia52672.2021.9532687","DOIUrl":"https://doi.org/10.1109/ITCIndia52672.2021.9532687","url":null,"abstract":"The test of digital circuits has benefitted greatly from the adoption of logical fault models and automatic test pattern generation (ATPG) tools targeting them. The cyclic process of defects in newer technology nodes being increasingly missed out by gross fault models and newer fault models being developed to better target them in silicon has continued, and EDA tools have evolved to provide new automation capabilities. This paper presents silicon results on one of Texas Instruments' new safety critical products which show unique defect detection with patterns targeting newer fault models like small delay defects (SDD) and cell aware faults (CAF), and RAM Sequential (RAM-S) ATPG patterns for memory faults. The net defective parts per million (DPPM) recovered using these methods is 72. Based on these results, recommendations for coverage targets and the order in which these faults must be targeted are provided. The unique silicon fall-out data presented in this paper provides a strategy for very low (zero) DPPM test of digital systems-on-chips (SoCs) in advanced technology nodes.","PeriodicalId":177825,"journal":{"name":"2021 IEEE International Test Conference India (ITC India)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115956838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Method and Apparatus for Bug Free Rapid Silicon Bringup 无虫快速硅培养方法及装置

2021 IEEE International Test Conference India (ITC India) Pub Date : 2021-07-18 DOI: 10.1109/ITCIndia52672.2021.9533001

Ravikumar Patel, A. Sivakumar, Ashutosh Anand, Kirankumar A Tatti, Prakash Kumar, Shokhi Rastogi

引用次数: 1

Adapting AI into Low Power Testing 将AI应用于低功耗测试

2021 IEEE International Test Conference India (ITC India) Pub Date : 2021-07-18 DOI: 10.1109/ITCIndia52672.2021.9532663

Hillol Maity, S. Chattopadhyay

{"title":"Adapting AI into Low Power Testing","authors":"Hillol Maity, S. Chattopadhyay","doi":"10.1109/ITCIndia52672.2021.9532663","DOIUrl":"https://doi.org/10.1109/ITCIndia52672.2021.9532663","url":null,"abstract":"11This work is partially supported by the research project sponsored by the Synopsys Inc., USAAdvancements in data science have enabled various fields to achieve unparalleled performance and efficiency enhancement. Different domains of Artificial Intelligence (AI) held the center of interest for researchers, academic and industrial practitioners throughout the last decade. When it comes to the low power testing, it still has a wide range of possibilities where existing methods and techniques can be made more efficient as well as faster with the integration of AI. In this proposal, first, we have come up with a new test vector reordering technique that attempts to reduce both shift and capture power during testing. Secondly, we claim that the use of AI models can significantly speed up such techniques where repeated simulation-based value estimation remains an essential bottleneck. We verify our claim by engaging a deep neural network (DNN) based predictive model to replace the repetitive simulation-based method on this new reordering technique. Experimental results show that the AI-based framework can speed up the simulation-based framework by 162 times, on average.","PeriodicalId":177825,"journal":{"name":"2021 IEEE International Test Conference India (ITC India)","volume":"176 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116642420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Comprehensive In-field Memory Self-Test and ECC Self-Checker -Minimal Hardware Solution for FuSa 综合现场内存自检和ECC自检- FuSa最小硬件解决方案

2021 IEEE International Test Conference India (ITC India) Pub Date : 2021-07-18 DOI: 10.1109/ITCIndia52672.2021.9532993

Ratheesh T. Veetil, Ramesh Sharma, Swapna Gundeboyina

{"title":"Comprehensive In-field Memory Self-Test and ECC Self-Checker -Minimal Hardware Solution for FuSa","authors":"Ratheesh T. Veetil, Ramesh Sharma, Swapna Gundeboyina","doi":"10.1109/ITCIndia52672.2021.9532993","DOIUrl":"https://doi.org/10.1109/ITCIndia52672.2021.9532993","url":null,"abstract":"As technology advances and System on Chip (SoC) become more complex, more and more embedded memories are packed inside the SoCs to cater the system requirements. Probability of malfunctioning of the device infield due to soft or hard defects in these memories and associated circuitry increase proportionally as well. As a result, in addition to testing and screening the product during manufacturing stage, the need for in-field testing of the memories has become critical to address Functional Safety (FuSa) requirements in mission critical industries such as automotive, medical and Artificial Intelligence (AI). In general, on most SoCs, Error Correcting Code (ECC) or parity checking schemes are implemented to detect and correct the error during memory access. Ensuring the correctness of the ECC operation in-field is also a safety critical requirement. This paper describes the methodology adopted for testing of embedded memories in safety critical SoCs and to verify the ECC logic in-filed with minimal hardware. In this proposed methodology, hardware and software system infrastructure is developed around industry standard memory test embedded instruments (Memory Built-In Self-Test controller and associated logic) to enable memory self-test and ECC logic testing during in-field usage. This paper describes the methodology adopted for testing of embedded memories in safety critical SoCs and to verify the ECC logic in-filed with minimal hardware. In this proposed methodology, hardware and software system infrastructure is developed around industry standard memory test embedded instruments (Memory Built-In Self- Test controller and associated logic) to enable memory self-test and ECC logic testing during in-field usage.","PeriodicalId":177825,"journal":{"name":"2021 IEEE International Test Conference India (ITC India)","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115181259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

An Efficient Test Architecture for Concurrent Over Voltage Stress Testing (OVST) of Logic and Memory 一种用于逻辑与存储器并行过电压应力测试(OVST)的高效测试架构

2021 IEEE International Test Conference India (ITC India) Pub Date : 2021-07-18 DOI: 10.1109/ITCIndia52672.2021.9532907

Snehil Agrawal, K. Pandey, Ravi Chandra Kumar Y, Anurag Jain

{"title":"An Efficient Test Architecture for Concurrent Over Voltage Stress Testing (OVST) of Logic and Memory","authors":"Snehil Agrawal, K. Pandey, Ravi Chandra Kumar Y, Anurag Jain","doi":"10.1109/ITCIndia52672.2021.9532907","DOIUrl":"https://doi.org/10.1109/ITCIndia52672.2021.9532907","url":null,"abstract":"Many of the latent defects in modern day SoCs don't get activated at the time of final package tests carried out under Adaptive Voltage Scaling (AVS) and rated functional operating frequencies. As a result, chips with latent defects too pass the final package testing. The latent defects become active during initial period of operation in the field causing serious long term reliability issues. High voltage stress tests, when deployed methodically accelerate the chip ageing and are quite efficient in exposing latent defects that lead to early life failures or infant mortality. It helps in catching unreliable parts before they are shipped to the customers. For set-top box SoCs, Overvoltage stress test (OVST) is performed at 1.4x of nominal device operating voltage for a duration of 200ms to 400ms. The desirable toggle coverage for logic and memories is 85% or greater to expose majority of the potential latent defect sites. These parameters can vary for different product lines and are arrived at by carefully using a robust methodology touched upon in this paper. This paper demonstrates how a JTAG pins based low pin count scan test infrastructure can be leveraged to achieve 85% toggle coverage across the entire digital portion of the SoC. The OVST architecture ensures all the memories are active along with logic thus both are tested concurrently in a single test. This scheme eliminates separate logic and memory OVST tests culminating into less than one-fourth of original test-time and avoids excessive over stressing of the device.","PeriodicalId":177825,"journal":{"name":"2021 IEEE International Test Conference India (ITC India)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123671022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Core Test Language based High Quality Memory Testing and Repair Methodology 基于核心测试语言的高质量内存测试与修复方法

2021 IEEE International Test Conference India (ITC India) Pub Date : 2021-07-18 DOI: 10.1109/ITCIndia52672.2021.9532722

Puneet Arora, Patrick R. Gallagher, S. Gregor

{"title":"Core Test Language based High Quality Memory Testing and Repair Methodology","authors":"Puneet Arora, Patrick R. Gallagher, S. Gregor","doi":"10.1109/ITCIndia52672.2021.9532722","DOIUrl":"https://doi.org/10.1109/ITCIndia52672.2021.9532722","url":null,"abstract":"Memories are highly structured and typically consume a large portion of the silicon within a design. As memories are highly dense and designed to the limits of the technology, they are more prone to failures than logic. Thus, memories concentrate a large majority of the defects. Several techniques have been established to target and detect defects within these memory instances and their interfacing logic. The techniques involve a systematic method of writing and reading data patterns to and from these memory instances. The IEEE 1450.6.2-2014 standard provides a documented means of describing the information required to enable memory built-in self-test (MBIST) hardware insertion and connection to the memories under test while providing the capability to utilize the most advanced memory testing techniques to test, perform failure analysis and, when redundant resources exist, repair these memories. MBIST models which strictly adhere to the IEEE 1450.6.2-2014 standard will enable EDA tool independence and provide consistent quality across all platforms. This paper describes some aspects of this standard and the challenges faced by memory providers, the producers of these models, while creating standard compliant MBIST models. The paper also describes the advantages of generating standard compliant MBIST models from the SoC designer and design implementation point of view along with MBIST tool providers, consumers of these models. The paper describes the Cadence Design Systems, Inc. environment comprising Genus, Modus, Xcelium and some standard utilities to enable the generation and validation of these views.","PeriodicalId":177825,"journal":{"name":"2021 IEEE International Test Conference India (ITC India)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124340905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Side-channel Analysis for Hardware Trojan Detection using Machine Learning 基于机器学习的硬件木马检测侧信道分析

2021 IEEE International Test Conference India (ITC India) Pub Date : 2021-07-18 DOI: 10.1109/ITCIndia52672.2021.9532888

Shuo Yang, Prabuddha Chakraborty, S. Bhunia

{"title":"Side-channel Analysis for Hardware Trojan Detection using Machine Learning","authors":"Shuo Yang, Prabuddha Chakraborty, S. Bhunia","doi":"10.1109/ITCIndia52672.2021.9532888","DOIUrl":"https://doi.org/10.1109/ITCIndia52672.2021.9532888","url":null,"abstract":"The evolving trend of the semiconductor supply chain resulted in a wide array of trust issues for electronic hardware. Among them, malicious alteration of designs in an untrusted design house or foundry, also known as hardware Trojan insertion, has emerged as a serious concern. A popular countermeasure against hardware Trojan attacks relies on identifying a Trojan fingerprint in a side - channel parameter. However, side - channel analysis suffers from (1) the process variations introduced in chips during fabrication and (2) the inability of conventional techniques to detect side - channel signatures of a small Trojan in a large design. In this paper, we propose a machine learning approach to detect malicious Trojan activities in a chip with high sensitivity. We use a custom - designed circuit board and measurements from several Trojan-inserted test chips for validating our proposed technique. We were able to detect Trojans with very high confidence and precision. Our method could detect extremely small Trojans of size as small as four gates with over 80% confidence. For larger Trojans, the prediction confidence is above 99%. We have also devised and implemented a framework for time - efficient automatic testing of a target chip using our method.","PeriodicalId":177825,"journal":{"name":"2021 IEEE International Test Conference India (ITC India)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132053677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

16x Multisite, High Current and High Power density Test Solution for Power Protection Device 16x多点、大电流、高功率密度电源保护器件测试解决方案

2021 IEEE International Test Conference India (ITC India) Pub Date : 2021-07-18 DOI: 10.1109/ITCIndia52672.2021.9532691

S. V, Gaurav Mittal

引用次数: 0

An Improved Test Pattern Reordering Framework Targeting Test Power Reduction 以降低测试功耗为目标的改进测试模式重新排序框架

2021 IEEE International Test Conference India (ITC India) Pub Date : 2021-07-18 DOI: 10.1109/ITCIndia52672.2021.9532684

Hillol Maity, S. Chattopadhyay, I. Sengupta, Parthajit Bhattacharya, Girish Patankar

引用次数: 0