An Efficient Test Architecture for Concurrent Over Voltage Stress Testing (OVST) of Logic and Memory

Abstract

Many of the latent defects in modern day SoCs don't get activated at the time of final package tests carried out under Adaptive Voltage Scaling (AVS) and rated functional operating frequencies. As a result, chips with latent defects too pass the final package testing. The latent defects become active during initial period of operation in the field causing serious long term reliability issues. High voltage stress tests, when deployed methodically accelerate the chip ageing and are quite efficient in exposing latent defects that lead to early life failures or infant mortality. It helps in catching unreliable parts before they are shipped to the customers. For set-top box SoCs, Overvoltage stress test (OVST) is performed at 1.4x of nominal device operating voltage for a duration of 200ms to 400ms. The desirable toggle coverage for logic and memories is 85% or greater to expose majority of the potential latent defect sites. These parameters can vary for different product lines and are arrived at by carefully using a robust methodology touched upon in this paper. This paper demonstrates how a JTAG pins based low pin count scan test infrastructure can be leveraged to achieve 85% toggle coverage across the entire digital portion of the SoC. The OVST architecture ensures all the memories are active along with logic thus both are tested concurrently in a single test. This scheme eliminates separate logic and memory OVST tests culminating into less than one-fourth of original test-time and avoids excessive over stressing of the device.