Core Test Language based High Quality Memory Testing and Repair Methodology

Abstract

Memories are highly structured and typically consume a large portion of the silicon within a design. As memories are highly dense and designed to the limits of the technology, they are more prone to failures than logic. Thus, memories concentrate a large majority of the defects. Several techniques have been established to target and detect defects within these memory instances and their interfacing logic. The techniques involve a systematic method of writing and reading data patterns to and from these memory instances. The IEEE 1450.6.2-2014 standard provides a documented means of describing the information required to enable memory built-in self-test (MBIST) hardware insertion and connection to the memories under test while providing the capability to utilize the most advanced memory testing techniques to test, perform failure analysis and, when redundant resources exist, repair these memories. MBIST models which strictly adhere to the IEEE 1450.6.2-2014 standard will enable EDA tool independence and provide consistent quality across all platforms. This paper describes some aspects of this standard and the challenges faced by memory providers, the producers of these models, while creating standard compliant MBIST models. The paper also describes the advantages of generating standard compliant MBIST models from the SoC designer and design implementation point of view along with MBIST tool providers, consumers of these models. The paper describes the Cadence Design Systems, Inc. environment comprising Genus, Modus, Xcelium and some standard utilities to enable the generation and validation of these views.