Method and Apparatus for Bug Free Rapid Silicon Bringup

Abstract

Today SoC designs are complex and dense with millions of transistors. These designs have complex DFT architecture for testing. Thousands of DFT patterns are used during silicon bring up. All these patterns are going through multiple stages of pre silicon verification to ensure bug free design and meet higher pass rate on silicon. In this paper, we will talk about DFT pre silicon validation flow enhancements at different stages to verify design quality and ensure patterns quality delivered for post silicon validation with maximum patterns passing without re-generation in short duration of post silicon testing. This paper talks about enhancement done across different stages of verification cycle to meet rapid silicon bring-up with zero post silicon DFT bugs.