2021 IEEE International Test Conference India (ITC India)最新文献_第2页

A Novel Method to measure PLL Bandwidth in a 5G RF transceiver 5G射频收发器锁相环带宽测量新方法

2021 IEEE International Test Conference India (ITC India) Pub Date : 2021-07-18 DOI: 10.1109/ITCIndia52672.2021.9532696

P. Nair, Dineej A

引用次数: 0

Addressing High Speed Memory Interface Test Quality Gaps in Shared Bus Architecture 解决共享总线架构中高速存储器接口测试质量差距的问题

2021 IEEE International Test Conference India (ITC India) Pub Date : 2021-07-18 DOI: 10.1109/ITCIndia52672.2021.9533002

Wilson Pradeep, R. Gottumukkala, S. Vooka

{"title":"Addressing High Speed Memory Interface Test Quality Gaps in Shared Bus Architecture","authors":"Wilson Pradeep, R. Gottumukkala, S. Vooka","doi":"10.1109/ITCIndia52672.2021.9533002","DOIUrl":"https://doi.org/10.1109/ITCIndia52672.2021.9533002","url":null,"abstract":"Recent trends in high performance SoCs (System-on-Chips) indicate a significant growth in memory content causing memory paths to be amongst the most critical paths in the designs. Hence, high quality memory interface tests are crucial in achieving low DPPM (defective parts per million) and better screening of parts. Shared bus interface is a typical memory architecture used in complex processor cores to enable memory testing along its true functional access path. In spite of that, certain gaps exist which limits covering all functional interfaces to memories in its entirety. In this paper, we propose a novel methodology to strategically identify specific high speed memory interfaces with test quality gaps and tactically target them through structural scan based tests along the longest path to enable screen for marginal defects. The proposed method deploys a composite slack based test method to achieve high test quality at a minimal test cost impact. Experimental results on a large design indicate significant reduction (67%) in the target fault set, which resulted in 65% reduction in test vectors (71% test time reduction) using the proposed schemes as compared to baseline methods used for structural memory sequential test.","PeriodicalId":177825,"journal":{"name":"2021 IEEE International Test Conference India (ITC India)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122712909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Parallel Field Test Architecture for Boot-ROMs in Safety-Critical SoCs 安全关键型soc中引导rom的并行现场测试体系结构

2021 IEEE International Test Conference India (ITC India) Pub Date : 2021-07-18 DOI: 10.1109/ITCIndia52672.2021.9532633

Nitesh Mishra, Nikita Naresh, Aravind Acharya

引用次数: 1

A Fast Robust Operation Mode invariant Frame-work for IR drop Prediction 一种快速鲁棒操作模式不变框架用于红外跌落预测

2021 IEEE International Test Conference India (ITC India) Pub Date : 2021-07-18 DOI: 10.1109/ITCIndia52672.2021.9532744

Utsav Jana, Gaurav Jain, Vineeth Kaimal, Nachiket Soman, Ankita Agarwal, Deepak Agrawal

{"title":"A Fast Robust Operation Mode invariant Frame-work for IR drop Prediction","authors":"Utsav Jana, Gaurav Jain, Vineeth Kaimal, Nachiket Soman, Ankita Agarwal, Deepak Agrawal","doi":"10.1109/ITCIndia52672.2021.9532744","DOIUrl":"https://doi.org/10.1109/ITCIndia52672.2021.9532744","url":null,"abstract":"IR drop is a physical phenomena affecting timing and logical operation of the circuits. As technology nodes shrink this has become an unavoidable menace and this effect is pronounced at high clock frequencies. Excessive IR drop is responsible for path delay defects. We propose a frame-work which can predict IR drop for different operating modes of the design including test mode. Test pattern IR drop analysis is done late in the design cycle and is time and resource consuming. Evaluation of IR drop depends on multi physics effects and is time consuming and expensive. Industry EDA tools such as Redhawk, PrimeRail, Totem are used for IR drop analysis. These tools often perform exhaustive power grid analysis to identify critical IR drop regions and Engineering Change Order(ECO) is performed to fix these potential violating instances. We propose a light weight scalable machine learning model which can predict final post-ECO IR drop based on the features from pre-ECO design. Since the pre-ECO design is very early into the project phase our ML model avoids multiple iterations to predict final post- ECO IR drop thus saving time. We have implemented our machine learning model for medium scale industrial design A containing a million cell instances for typical typical (TT) corner at 0.945v. Early experiments on our industrial designs show coefficient of determination is 0.828 for the final IR drop prediction model. This model can save significant amount of time and cost while predicting the post- ECO design features and fixing the IR drop problem across functional and test mode.","PeriodicalId":177825,"journal":{"name":"2021 IEEE International Test Conference India (ITC India)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127946355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0