Addressing High Speed Memory Interface Test Quality Gaps in Shared Bus Architecture

Abstract

Recent trends in high performance SoCs (System-on-Chips) indicate a significant growth in memory content causing memory paths to be amongst the most critical paths in the designs. Hence, high quality memory interface tests are crucial in achieving low DPPM (defective parts per million) and better screening of parts. Shared bus interface is a typical memory architecture used in complex processor cores to enable memory testing along its true functional access path. In spite of that, certain gaps exist which limits covering all functional interfaces to memories in its entirety. In this paper, we propose a novel methodology to strategically identify specific high speed memory interfaces with test quality gaps and tactically target them through structural scan based tests along the longest path to enable screen for marginal defects. The proposed method deploys a composite slack based test method to achieve high test quality at a minimal test cost impact. Experimental results on a large design indicate significant reduction (67%) in the target fault set, which resulted in 65% reduction in test vectors (71% test time reduction) using the proposed schemes as compared to baseline methods used for structural memory sequential test.