Parallel Field Test Architecture for Boot-ROMs in Safety-Critical SoCs

Abstract

In safety-critical automotive devices with functional Read-only-memories (ROMs), boot-up time and periodic check of correctness of the ROM code is of utmost importance for the overall operation of the device from safety perspective. Current solutions use a hardware/software Cyclic Redundancy Check (CRC) to validate the ROM contents. However, CRC comes with a significant test time overhead, which can impact the boot-up time of device. In this paper, we present a novel non-destructive field-test architecture which validates the ROM contents parallelly and reduces test-time significantly by 99% as compared to native CRC. We also present a novel methodology using which we can perform parallel test on boot-ROMs without disturbing the boot flow during power-up.