An Improved Test Pattern Reordering Framework Targeting Test Power Reduction

Abstract

Next-generation devices are expected to have higher mobility, which forces the device packaging to be small. Small devices enforce stringent power requirements for the embedded VLSI circuits. In the test mode, these circuits dissipate more power compared to the normal mode of operation. The proposed framework in this paper provides an improved solution to reduce the test power by maintaining a proper ordering of the input test patterns. A modified Kernighan-Lin (KL) graph partitioning algorithm has been used for the reordering problem. This technique assumes the circuit under test (CUT) to be a combinational or full scan sequential circuit. When tested against ISCAS'89 benchmark circuits, our framework can reduce the power dissipation better than greedy heuristics as well as some previously reported works without affecting the fault coverage. This framework also takes care of the factors that may affect the quality of the end solution.