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2023 IEEE International Symposium on Circuits and Systems (ISCAS)最新文献

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A 32 Gb/s, 0.42 pJ/bit Passive Hybrid Simultaneous Bidirectional Transceiver for Die-to-Die Links 一种32 Gb/s, 0.42 pJ/bit无源混合同时双向收发器
2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181991
Durand Jarrett-Amor, Kunal Yadav, D. Zhang, Bangda Yang, Sadegh Jalali, A. C. Carusone
{"title":"A 32 Gb/s, 0.42 pJ/bit Passive Hybrid Simultaneous Bidirectional Transceiver for Die-to-Die Links","authors":"Durand Jarrett-Amor, Kunal Yadav, D. Zhang, Bangda Yang, Sadegh Jalali, A. C. Carusone","doi":"10.1109/ISCAS46773.2023.10181991","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10181991","url":null,"abstract":"This paper presents a single-ended, passive hybrid for a simultaneous bidirectional (SBD) die-to-die link. It provides a signal-to-interference ratio better than 20 dB at 10 GHz while consuming only 3.72% of the total power and is used in a split-termination SBD transceiver (TRX) with a transimpedance amplifier (TIA) as a driver, which improves signal integrity by minimizing signal reflections. Extracted simulations of the TRX in 16nm CMOS over a 5 mm die-to-die link demonstrate error-free communication at 32 Gbps (16 Gbps + 16 Gbps) with a power efficiency of 0.42 pJ/bit on a 0.9 V. supply.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122251999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 129.83 TOPS/W Area Efficient Digital SOT/STT MRAM-Based Computing-In-Memory for Advanced Edge AI Chips 基于129.83 TOPS/W高效率数字SOT/STT mram的先进边缘人工智能芯片内存计算
2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181328
Lu Lu, Aarthy Mani, A. Do
{"title":"A 129.83 TOPS/W Area Efficient Digital SOT/STT MRAM-Based Computing-In-Memory for Advanced Edge AI Chips","authors":"Lu Lu, Aarthy Mani, A. Do","doi":"10.1109/ISCAS46773.2023.10181328","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10181328","url":null,"abstract":"This paper proposes a spin-orbit torque (SOT) magnetoresistive random access memory (MRAM)-based digital computing in memory (CIM) structure for advanced CIM edge AI chips. To avoid frequent data reloading and reduce the area overhead caused by the large transistor in the write path, 11 transistors and 4 shared heavy metal (HM) SOT MRAM bitcell is proposed. It contains 4b weight in a single cell in a compact area able to hold a large capacity with reduced latency. Compared to the previous SRAM+NOR digital CIM design, the SOT/STT MRAM CIM designs occupy only 40% and 30% bitcell area respectively. Additionally, SOT MRAM has a 1.16% leakage current of SRAM at the TT corner at room temperature. The proposed design is verified using statistic simulations in 28nm technology. It achieves 129.83 TOPS/W at 1b/1b/8b precision.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129705562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 3D-Printed Fourth-Order Stacked Filter for Integrated DC-DC Converters 用于集成DC-DC转换器的3d打印四阶堆叠滤波器
2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10182210
Jin-Hui Lee, V. Adrian, S. Tay, Yanshan Xie, B. Gwee, J. Chang
{"title":"A 3D-Printed Fourth-Order Stacked Filter for Integrated DC-DC Converters","authors":"Jin-Hui Lee, V. Adrian, S. Tay, Yanshan Xie, B. Gwee, J. Chang","doi":"10.1109/ISCAS46773.2023.10182210","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10182210","url":null,"abstract":"The passive devices in state-of-the-art miniaturized switched-mode DC-DC converters are generally integrated by means of on-chip and in-package methods. Nevertheless, the quality is poor-to-moderate, thereby compromising the power-efficiency. In this paper, we propose the miniaturization of the DC-DC converter by means of realizing its passive devices as embedded devices that are printed within a high-density 3D inkjet printed-circuit-board (PCB). We propose a fourth-order stacked LC filter embodying passive components with small values-effectively at no additional cost because they are embedded through 3D-printing. For the inductor and capacitor, we propose to adopt a high- $Q$ solenoidal structure and the metal-insulator-metal planar structure, respectively. The proposed filter is printed within the 3D-PCB with a compact 124 mm3volume due to the stacked arrangement. The measured AC attenuation is 21.2 dB at 200 MHz. The filter is further verified by means of computer simulations of a DC-DC buck converter. Simulation results of the converter employing the filter show a low output voltage ripple at 146 mV and a high peak power-efficiency of ~78% at 200 MHz switching frequency with 150 mA load current.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129810034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Gaussian Process for Nonlinear Regression via Memristive Crossbars 忆阻横条非线性回归的高斯过程
2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181785
Gianluca Zoppo, Anil Korkmaz, Francesco Marrone, Su-in Yi, S. Palermo, F. Corinto, R. S. Williams
{"title":"Gaussian Process for Nonlinear Regression via Memristive Crossbars","authors":"Gianluca Zoppo, Anil Korkmaz, Francesco Marrone, Su-in Yi, S. Palermo, F. Corinto, R. S. Williams","doi":"10.1109/ISCAS46773.2023.10181785","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10181785","url":null,"abstract":"Over the last decade, Gaussian processes (GPs) have become popular in the area of machine learning and data analysis for their flexibility and robustness. Despite their attractive formulation, practical use in large-scale problems remains out of reach due to computational complexity. Existing direct computational methods for manipulations involving large-scale $ntimes n$ covariance matrices require $O(n^{3})$ calculations. In this work, we present the design and evaluation of a simulated computing platform for exact GP inference, that achieves true model parallelism using memristive crossbars. To achieve a one-shot solution, a linear equation solver and a vector-matrix multiplication solver crossbar configurations are used together, reducing the number of operations from $O(n^{3})$ to $O(n)$. The transistor level op-amps, ADC models for quantization, circuit and interconnect parasitics, together with the finite memristor precision are incorporated into the system simulation. The analog system resulted in %1.51 mean error and %2.93 average variance error in solving a nonlinear regression problem. The proposed method achieved 9× to 144× better energy efficiency compared to TPU and 7× compared to a custom analog linear regression solver.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128302366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Depletion Based Digital and Analogue Circuits with n-Channel IGZO Thin Film Transistors 基于损耗的n通道IGZO薄膜晶体管数字和模拟电路
2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181633
G. Carvalho, M. Pereira, A. Kiazadeh, V. Tavares
{"title":"Depletion Based Digital and Analogue Circuits with n-Channel IGZO Thin Film Transistors","authors":"G. Carvalho, M. Pereira, A. Kiazadeh, V. Tavares","doi":"10.1109/ISCAS46773.2023.10181633","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10181633","url":null,"abstract":"In this work, both analogue and digital depletion-mode single channel transistor circuits are presented and are simulated using an n-channel IGZO technology with $boldsymbol{V}_{boldsymbol{TH}}= -mathrm{0}.mathbf{87}mathbf{V}$. A logic family is introduced, suppressing the need for an additional voltage level and level restoring circuitry. Furthermore, in the analogue domain, a depletion current mirror topology is presented with demonstrated small current error. Finally, the current mirror is used in the design of an OpAmp, achieving a simulated open-loop gain of 45 dB, CMRR of 58 dB, unity-gain frequency of 444 kHz and a phase margin of 71 degrees.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128392835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Low-Power Neuromorphic CMOS Delta-Sigma Modulator Featuring Tunable Background Attenuation and Potentiostatic Asynchronous Readout for Smart Amperometric Electrochemical Sensors 一种低功耗神经形态CMOS Delta-Sigma调制器，具有可调背景衰减和恒电位异步读出功能，用于智能安培电化学传感器
2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10182093
Javier Cuenca-Michans, Joan Aymerich, L. Terés, C. Jiménez-Jorquera, F. Serra-Graells, J. M. Margarit-Taulé
{"title":"A Low-Power Neuromorphic CMOS Delta-Sigma Modulator Featuring Tunable Background Attenuation and Potentiostatic Asynchronous Readout for Smart Amperometric Electrochemical Sensors","authors":"Javier Cuenca-Michans, Joan Aymerich, L. Terés, C. Jiménez-Jorquera, F. Serra-Graells, J. M. Margarit-Taulé","doi":"10.1109/ISCAS46773.2023.10182093","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10182093","url":null,"abstract":"This paper presents a neuromorphic CMOS Delta-Sigma modulator for the robust and energy-efficient readout of amperometric electrochemical sensors. The circuit makes use of an adaptive integrate-and-fire scheme to deliver asynchronous A/D conversion and attenuation of background currents with minimal power requirements. The modulator reuses the dynamic characteristics of the electrode-electrolyte interface for quantization noise shaping, and it offers potentiostatic control of the voltage difference between working and reference electrodes of a three-electrode electrochemical cell. Electrical simulation results are reported at transistor level for a smart electrochemical sensor currently being integrated in a 1.2-V 65-nm 9-metal CMOS technology. The frontend exhibits a tunable off-band rejection of 20 dB with a peak SNR of 61dB and $70-mumathrm{W}$ power consumption.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128759650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 12.9-38.6-GHz CMOS LNA With Triple-Coupled Transformer-Based Input Matching Technique 基于三耦合变压器输入匹配技术的12.9-38.6 ghz CMOS LNA
2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10182098
Bihong Zhang, Hongyu Mao, Xiaolong Liu
{"title":"A 12.9-38.6-GHz CMOS LNA With Triple-Coupled Transformer-Based Input Matching Technique","authors":"Bihong Zhang, Hongyu Mao, Xiaolong Liu","doi":"10.1109/ISCAS46773.2023.10182098","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10182098","url":null,"abstract":"This paper presents a wideband millimeter-wave low-noise amplifier (LNA) in a 65-nm CMOS process. A triple-coupled transformer-based input matching technique is proposed to enhance the input power matching bandwidth. In addition, by leveraging a transformer between the two-stage common source (CS) amplifiers, the noise figure (NF) is reduced while the transconductance of the second stage is improved to extend the gain bandwidth. The proposed LNA is designed to achieve an ultra-wide 10-dB return loss bandwidth from 12.4 to 46.9 GHz. The effective input matching bandwidth is limited by the 3-dB gain bandwidth, which is from 12.9 to 38.6 GHz. It achieves a peak gain of 11.9 dB and a minimum NF of 3.2 dB. The third-order input intercept point (IIP3) is −0.45 dBm at 30 GHz. The proposed LNA occupies a core area of 0.18 mm2 and consumes only 5.1 mW.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128761649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Thresholding based Stochastic Robust Algorithm for Distributed Compressed Sensing 基于阈值的分布式压缩感知随机鲁棒算法
2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181386
Ketan Atul Bapat, M. Chakraborty
{"title":"Thresholding based Stochastic Robust Algorithm for Distributed Compressed Sensing","authors":"Ketan Atul Bapat, M. Chakraborty","doi":"10.1109/ISCAS46773.2023.10181386","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10181386","url":null,"abstract":"In this paper, we first present a stochastic gradient based robust algorithm for recovering a sparse signal from compressed measurements corrupted by impulsive noise for large problems where calculation of the full gradient is expensive. This stochastic gradient based strategy is then modified and applied to diffusion based distributed compressed sensing. In the proposed algorithm, a proxy to the actual gradient is found and hard thresholding based updates are carried out. The proposed algorithm uses Lorentzian norm of the residual as the cost function, making it robust against impulsive noise. It is observed through simulations that the proposed algorithm is able to outperform existing stochastic gradient based algorithms and is able to provide at par recovery performance to that of other robust deterministic algorithms currently available in literature for distributed compressed sensing.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129048330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An 18.5nW, 62.9dB PSRR, Switched-Capacitor Bandgap Voltage Reference using Low Power Clock Generator Circuit for Biomedical Applications 一种18.5nW, 62.9dB PSRR，基于低功率时钟发生器的开关电容带隙基准电压电路，用于生物医学应用
2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181473
Samriddhi Agarwal, Shameer Basha Yerragudi, Naveen Dasari, Inhee Lee, Zia Abbas
{"title":"An 18.5nW, 62.9dB PSRR, Switched-Capacitor Bandgap Voltage Reference using Low Power Clock Generator Circuit for Biomedical Applications","authors":"Samriddhi Agarwal, Shameer Basha Yerragudi, Naveen Dasari, Inhee Lee, Zia Abbas","doi":"10.1109/ISCAS46773.2023.10181473","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10181473","url":null,"abstract":"This paper proposes a switched-capacitor network (SCN) based fractional bandgap voltage reference (BGR) circuit designed in 180nm CMOS process to achieve high accuracy and low power consumption for implantable biomedical applications. The design proposes a $V_{EB}$ generator that employs a 2x charge pump and an improved SCN to generate a temperature inde-pendent reference voltage $(V_{REF})$’. A low-power clock generator circuit is proposed, which reduces the leakage current by 37 % compared to previous works, thereby reducing the circuit's power consumption to 18.5nW at typical conditions. The design works from a supply voltage of 0.5V and has a TC of 74. Sppm/ ${}^{circ} mathrm{C}$ over a temperature range of $0-80^{circ} mathrm{C}$. The PSRR of the circuit is -62.9dB at 100Hz. Based on the Monte Carlo simulations of 500 samples, we obtain an untrimmed $3sigma/mu$ of 2.6%. The design occupies an active area of 0.027mm2.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130304586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On the Genome Sequence Alignment FPGA Acceleration via KSW2z 基于KSW2z的基因组序列比对FPGA加速研究
2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181600
Alberto Zeni, Guido Walter Di Donato, Alessia Della Valle, F. Carloni, M. Santambrogio
{"title":"On the Genome Sequence Alignment FPGA Acceleration via KSW2z","authors":"Alberto Zeni, Guido Walter Di Donato, Alessia Della Valle, F. Carloni, M. Santambrogio","doi":"10.1109/ISCAS46773.2023.10181600","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10181600","url":null,"abstract":"Pairwise sequence alignment is a fundamental step for many genomics and molecular biology applications. Given the quadratic time complexity of alignment algorithms, the community demands innovative, fast, and efficient techniques to perform this task. Furthermore, general-purpose architectures lack the necessary performance to address the computational load of these algorithms. In this context, we present the first open-source FPGA implementation of the popular KSW2z algorithm employed by minimap2. Our design also implements the $Z- mathbf{drop}$ heuristic and banded alignment as the original software to further reduce the processing time if needed. The proposed multi-core accelerator achieves up to $mathbf{7.70}times$ improvement in speedup and $mathbf{20.07}times$ in energy efficiency compared to the multi-threaded software implementation run on a Xeon Platinum 8167M processor.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123347583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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