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2023 IEEE International Symposium on Circuits and Systems (ISCAS)最新文献

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A Metastability Inference and Avoidance Technique for Near-Threshold-Voltage Network-on-Chip 近阈值电压片上网络的亚稳态推断与避免技术
2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181952
Lin Shao, M. Lai, Shi Xu, Chuxiong Lin, Weifeng He
{"title":"A Metastability Inference and Avoidance Technique for Near-Threshold-Voltage Network-on-Chip","authors":"Lin Shao, M. Lai, Shi Xu, Chuxiong Lin, Weifeng He","doi":"10.1109/ISCAS46773.2023.10181952","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10181952","url":null,"abstract":"With the application of low-power design technologies such as dynamic voltage and frequency scaling (DVFS) and globally asynchronous locally synchronization (GALS), a multi-voltage-/frequency-domain network-on-chip (NoC) suffers more and more serious metastability issue in inter-core data communication. To mitigate the metastability during the clock-domain crossing, a technique titled metastability inference and avoidance (MIAA) is presented. MIAA infers the potential metastability risk of a synchronizer's sampling clock through phase detection of a phase-related clock. MIAA avoids the occurrence of metastability by adaptively modulating the clock phase of the sampling clock once it infers the potential metastability risk. We designed a MIAA-based 40nm GALS $2times 2$ NoC that contains four independent voltage/frequency domains. The post-layout simulation results show that MIAA can well predict the metastability risks and reduce the probability of metastability to zero across a wide range of frequency ratios. The metastability mitigation allows us to use a single flip-flop instead of a multi-stage synchronizer for synchronization in the NoC, thereby improving the latency and throughput of the NoC by 40.2% and 79%, respectively.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126637135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Improved Chroma From Luma Intra Prediction Mode Beyond AV1 改进色度从亮度内预测模式超越AV1
2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181381
Jing Ye, Liang Zhao, Xin Zhao, Shanchun Liu
{"title":"Improved Chroma From Luma Intra Prediction Mode Beyond AV1","authors":"Jing Ye, Liang Zhao, Xin Zhao, Shanchun Liu","doi":"10.1109/ISCAS46773.2023.10181381","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10181381","url":null,"abstract":"In AV1, Chroma from Luma (CfL) intra prediction mode is adopted to predict chroma samples by exploiting the linear correlation between the co-located samples of luma and chroma components, wherein the scaling factor of the linear model is transmitted to the decoder side and the offset factor is derived as the average of neighboring chroma pixels. In this paper, the CfL prediction mode is improved in following three aspects. Firstly, the calculation of DC contribution between luma and chroma is aligned to improve the accuracy of CfL prediction. Secondly, to further enhance the CfL prediction mode, a new cross-component intra prediction mode without signaling of scaling factor is employed. Thirdly, the down-sampling filter for CfL mode is adaptively selected at the encoder side for each video sequence. Simulation results show that, on top of AOMedia Video Model (AVM) v3.0.0, an average coding gain of 0.9%, 0.5%, and 0.4% in terms of YUV-PNSR is achieved for all intra, random access, and low delay configurations, respectively.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126733099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
SaGNN: a Sample-based GNN Training and Inference Hardware Accelerator 基于样本的GNN训练和推理硬件加速器
2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10182227
Haoyang Wang, Shengbing Zhang, Kaijie Feng, Miao Wang, Zhao Yang
{"title":"SaGNN: a Sample-based GNN Training and Inference Hardware Accelerator","authors":"Haoyang Wang, Shengbing Zhang, Kaijie Feng, Miao Wang, Zhao Yang","doi":"10.1109/ISCAS46773.2023.10182227","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10182227","url":null,"abstract":"Graph neural networks (GNNs) operations contain a large number of irregular data operations and sparse matrix multiplications, resulting in the under-utilization of computing resources. The problem becomes even more complex and challenging when it comes to large graph training. Scaling GNN training is an effective solution. However, the current GNN operation accelerators do not support the mini-batch structure. We analyze the GNN operational characteristics from multiple aspects and take both the acceleration requirements in the GNN training and inference process into account, and then propose the SaGNN system structure. SaGNN offers multiple working modes to provide acceleration solutions for different GNN frameworks while ensuring system configurability and scalability. Compared to related works, SaGNN brings 5.0x improvement in system performance.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126932743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Tunable $LC$ resonator for multiplexed multi-qubit readout 用于多路多量子位读出的可调谐LC谐振器
2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10182075
Llorenç Fanals, E. Alarcon, Imran Bashir, E. Blokhina, Dirk R. Leipold, R. Staszewski
{"title":"Tunable $LC$ resonator for multiplexed multi-qubit readout","authors":"Llorenç Fanals, E. Alarcon, Imran Bashir, E. Blokhina, Dirk R. Leipold, R. Staszewski","doi":"10.1109/ISCAS46773.2023.10182075","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10182075","url":null,"abstract":"This paper proposes the use of a tunable $LC$ resonator to read an array of qubits in a multiplexed fashion, by making the dispersive shift of the targeted qubit dominant. Cavity and circuit electrodynamics (QED) theory is shown to support this idea. The tunable capacitor array, in parallel with a superconducting inductance, is designed to maximize the quality factor by frequency range product, $QcdotDeltaomega$. This approach only requires one RF signal to measure multiple qubits, which can facilitate quantum computing scaling.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116419225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Adaptive Probability Estimation Techniques for Context Adaptive Arithmetic Coding 上下文自适应算术编码的自适应概率估计技术
2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10182208
M. Krishnan, Xin Zhao, Shanchun Liu
{"title":"Adaptive Probability Estimation Techniques for Context Adaptive Arithmetic Coding","authors":"M. Krishnan, Xin Zhao, Shanchun Liu","doi":"10.1109/ISCAS46773.2023.10182208","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10182208","url":null,"abstract":"Context-adaptive arithmetic coding is an essential entropy coding scheme used in all modern video codecs. An arithmetic coder with binary symbol size is used by video codecs like H.264/AVC, HEVC and VVC while AV1 utilizes an arithmetic coder with syntax adaptive M-ary symbols. Recently, the Alliance for Open Media (AOMedia) has initiated exploration activities towards next-generation video coding tools beyond AV1. In this regard, improvements on probability estimation techniques for the context-adaptive M-ary arithmetic coder in AV1, are explored in this paper. The proposed improvements are applied and tested on top of the reference implementation of the exploratory codec beyond AV1, known as AVM (AOMedia Video Model). Experimental results show that, compared to AVM, the proposed method achieves an average 0.27%, 0.34% and 0.32% overall BD-rate coding gains for All Intra (AI), Random Access (RA) and Low Delay (LD) coding configurations for a wide range of video content.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116420716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Improved method to join BDDs for incompletely specified Boolean functions 为不完全指定布尔函数联接bdd的改进方法
2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181893
Renato D. Peralta, Joao P. Nespolo, P. Butzen, M. Kolberg, A. Reis
{"title":"An Improved method to join BDDs for incompletely specified Boolean functions","authors":"Renato D. Peralta, Joao P. Nespolo, P. Butzen, M. Kolberg, A. Reis","doi":"10.1109/ISCAS46773.2023.10181893","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10181893","url":null,"abstract":"An incompletely specified Boolean function, also known as a Boolean relation, can be described by any combination of its on-set, off-set, and don't care (DC) set pairs. To transform a Boolean relation into a Boolean function (fully specified), we have to assign the DCs from the original specification. Depending on the DCs assignment, a better function minimization may result from the original specification. This article presents a method for joining two BDDs by describing the on-set and off-set of an incompletely specified $f$ function into a single BDD for a fully specified coverage of the function. The proposed method is compared with the Restrict, Constrain and LICompaction methods implemented by the CUDD package, which are references for this problem using BDDs. In addition to these methods, we also compare our results with the Join method, which is a more recent proposal for the problem of assigning and minimizing incompletely specified Boolean functions. The LI-Compaction method presented the largest number of BDD nodes among the analyzed methods. Compared to the LICompaction method, the Restrict method produced 2.12% fewer nodes, the Constrain and Join methods produced 1.95% fewer nodes, while our method produced 24.80% fewer nodes.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116576897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
In-material reservoir implementation of reservoir-based convolution 储层内基于储层的卷积实现
2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181436
Yuichiro Tanaka, Y. Usami, Hirofumi Tanaka, H. Tamukoh
{"title":"In-material reservoir implementation of reservoir-based convolution","authors":"Yuichiro Tanaka, Y. Usami, Hirofumi Tanaka, H. Tamukoh","doi":"10.1109/ISCAS46773.2023.10181436","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10181436","url":null,"abstract":"This study aims to implement a reservoir-based convolutional neural network (CNN) on physical reservoir computing (RC) to develop an efficient image recognition system for edge AI. Therefore, we propose a novel reservoir-based convolution circuit system that uses in-material reservoir computing, a type of physical RC made from a sulfonated polyaniline network. The experimental results demonstrate that the proposed circuit system extracts image features in the same way as the original CNN and that a reservoir-based CNN on the in-material RC achieves an accuracy rate of 81.7% in an image classification task while an echo state network-based CNN achieves 87.7%.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122778846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Live Demonstration: Real-time Multi-modal Hearing Assistive Technology Prototype 现场演示:实时多模态助听技术原型
2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10182070
M. Gogate, Adeel Hussain, K. Dashtipour, Amir Hussain
{"title":"Live Demonstration: Real-time Multi-modal Hearing Assistive Technology Prototype","authors":"M. Gogate, Adeel Hussain, K. Dashtipour, Amir Hussain","doi":"10.1109/ISCAS46773.2023.10182070","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10182070","url":null,"abstract":"Hearing loss affects at least 1.5 billion people globally. The WHO estimates 83% of people who could benefit from hearing aids do not use them. Barriers to HA uptake are multifaceted but include ineffectiveness of current HA technology in noisy environments with multiple competing noise sources where human performance is known to be dependent upon input from both the aural and visual senses.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123019173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Neural Stimulator with 11.4 V Voltage-Compliance Realized in a $0.18-mumathrm{m}$ 3.3 V CMOS Technology 用$0.18-mumath {m}$ 3.3 V CMOS技术实现11.4 V电压顺应神经刺激器
2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10182112
Liwei Cao, Xiao Liu
{"title":"A Neural Stimulator with 11.4 V Voltage-Compliance Realized in a $0.18-mumathrm{m}$ 3.3 V CMOS Technology","authors":"Liwei Cao, Xiao Liu","doi":"10.1109/ISCAS46773.2023.10182112","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10182112","url":null,"abstract":"A neural stimulator with a 11.4 V voltage compliance under a 12 V supply voltage has been proposed. The stimulator ASIC has been realized using only low-voltage transistors in a $0.18-mumathrm{m}$ 3.3 V triple-well CMOS process with deep N-well. The proposed stimulator continuously senses the voltage at the stimulating electrode and adaptively adjusts the bias voltages to the gate of stacked transistors in the output branch, ensuring the voltage stress on each individual transistor are all within the safety limit. The stimulator supplies biphasic stimulus current with a maximum stimulus current of $100 mumathrm{A}$ and occupies 0.08 mm2 area. The proposed low-voltage transistor implementation of a high-voltage stimulator is especially suitable for multi-channel closed-loop neuroprosthetic devices where the stimulator can be integrated with other units which typically operate from low voltage supplies, such as recording amplifiers and signal processing units.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"20 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114276348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Open-Source $4 times 8$ Coarse-Grained Reconfigurable Array Using SkyWater 130 nm Technology and Agile Hardware Design Flow 基于SkyWater 130纳米技术和敏捷硬件设计流程的开源4 × 8$粗粒度可重构阵列
2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10182052
Po-Han Chen, Charles Tsao, Priyanka Raina
{"title":"An Open-Source $4 times 8$ Coarse-Grained Reconfigurable Array Using SkyWater 130 nm Technology and Agile Hardware Design Flow","authors":"Po-Han Chen, Charles Tsao, Priyanka Raina","doi":"10.1109/ISCAS46773.2023.10182052","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10182052","url":null,"abstract":"With the end of Dennard scaling, hardware specialization has been broadly adopted in computing systems to improve performance and energy-efficiency. However, specialized hardware deprecates soon after new algorithms are introduced. A coarse-grained reconfigurable array (CGRA) offers the programmability required for accommodating application changes, while still being more efficient than FPGAs and GPUs. This work presents a $4times 8$ CGRA created using an open-source agile hardware-compiler co-design framework. This is the first CGRA chip designed using the open-source SkyWater 130nm technology and OpenRAM memory compiler. We present the CGRA architecture, implementation results, and silicon validation results to verify the technology portability of agile hardware design framework.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114420565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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