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2023 IEEE International Symposium on Circuits and Systems (ISCAS)最新文献

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Experimental Characterisation of Drift on ISFET Arrays and its pH Dependence ISFET阵列漂移的实验表征及其pH依赖性
2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181716
Costanza Gulli, Nicolas Moser, P. Georgiou
{"title":"Experimental Characterisation of Drift on ISFET Arrays and its pH Dependence","authors":"Costanza Gulli, Nicolas Moser, P. Georgiou","doi":"10.1109/ISCAS46773.2023.10181716","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10181716","url":null,"abstract":"This paper presents an experimental characterisation of the pH dependence of drift on ISFET sensors. Experiments are run on an array of over 4000 sensors fabricated in commercial CMOS technology with pH buffer solutions of known pH. A mathematical model is built and the fitted coefficients are compared between experiments where the pH is constant and where pH changes. An exponential and a linear model are compared, as well as different metrics for coefficient comparison. It is shown that a dependence can be found between drift and pH variation when drift rate exceeds $15mu V/s$. This serves as a first step towards the development of a new metric to aid classification of nucleic acid amplification experiments.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126804505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 94.6dB-SNDR 50kHz-BW 1-1-1 MASH ADC Using OTA-FIA Based Integrators 基于OTA-FIA集成商的94.6dB-SNDR 50kHz-BW 1-1-1 MASH ADC
2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181887
Xirui Hao, Junsheng Chen, Lingxin Meng, Menglian Zhao, Z. Tan
{"title":"A 94.6dB-SNDR 50kHz-BW 1-1-1 MASH ADC Using OTA-FIA Based Integrators","authors":"Xirui Hao, Junsheng Chen, Lingxin Meng, Menglian Zhao, Z. Tan","doi":"10.1109/ISCAS46773.2023.10181887","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10181887","url":null,"abstract":"This paper presents a novel two-stage amplifier, which cascades a duty-cycled inverter-based OTA and a floating-inverter amplifier (FIA). The proposed OTA-FIA can achieve 72.0dB gain under a 1.2V supply, whose output swing is 420mV. Additionally, it exhibits intrinsic loop stability without compensation and reduces thermal noise during integration. The proposed OTA-FIA is adopted in a low distortion 1-1-1 MASH structure to obtain high resolution. Simulated in a 55 nm CMOS process, the proposed ADC can achieve an SNDR of 94.6dB with a bandwidth of 50kHz. It consumes $363.8mu mathrm{W}$ from a 1.2V supply at a 5MS/s sampling frequency, resulting in a 176.0dB SNDR-based Schreier FoM.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115299885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 15.9 mW 96.5 fps Memory-Efficient 3D Reconstruction Processor with Dilation-based TSDF Fusion and Block-Projection Cache System 基于膨胀的TSDF融合和块投影缓存系统的15.9 mW 96.5 fps高效内存3D重建处理器
2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181660
Hankyul Kwon, Gwangtae Park, Junha Ryu, Wooyoung Jo, H. Yoo
{"title":"A 15.9 mW 96.5 fps Memory-Efficient 3D Reconstruction Processor with Dilation-based TSDF Fusion and Block-Projection Cache System","authors":"Hankyul Kwon, Gwangtae Park, Junha Ryu, Wooyoung Jo, H. Yoo","doi":"10.1109/ISCAS46773.2023.10181660","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10181660","url":null,"abstract":"A real-time dense 3D reconstruction on lightweight AR headsets is challenging since its memory access surpasses the available memory bandwidth. To solve this problem, the proposed processor integrates two key building blocks - Dilation-based TSDF (D-TSDF) fusion and Block-Projection (BP) engine. D-TSDF projects the depth map in the reverse order of voxel-to-pixel coordinate transformation and dilates it, leading to 96.61% External Memory Access (EMA) reduction with minimum map quality degradation. Second, a specialized BP engine compresses high-resolution occupancy grid by decomposing the 3D bitmap into 2D and 1D vectors, achieving $times mathbf{166.09}$ reduced memory bandwidth. The proposed processor is implemented in 28nm CMOS technology occupying 1.27 mm2 area. As a result, 96.45 fps 3D reconstruction is possible while consuming only 15.94 mW power.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115316291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High Linearity Front-End Circuit for RF Sampling ADCs with Nonlinear Junction Capacitor Cancellation 具有非线性结电容抵消的射频采样adc的高线性前端电路
2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181839
Yihang Cheng, Yaning Wang, Fule Li, Chun Zhang, Zhihua Wang
{"title":"High Linearity Front-End Circuit for RF Sampling ADCs with Nonlinear Junction Capacitor Cancellation","authors":"Yihang Cheng, Yaning Wang, Fule Li, Chun Zhang, Zhihua Wang","doi":"10.1109/ISCAS46773.2023.10181839","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10181839","url":null,"abstract":"This paper presents a high linearity front-end circuit for RF sampling ADCs, including an input buffer and a sampling network. The input buffer uses a two-stage NMOS cascode structure and is powered by a separate LDO to support a larger signal swing input with high power supply rejection (PSR) and linearity. We use bootstrap switch with bulk-switching techniques to ensure sampling linearity, while a feed-through compensation technique with self-cancellation of nonlinear junction capacitor is applied to achieve better performance at high-frequency inputs. The above techniques are validated at a 1GS/s ADC in 65nm process, and the simulation results show that the low-frequency PSR of the input buffer reaches over 120dB, and the SNR, SNDR and SFDR of the overall front-end circuit are 78.74dB, 72.37dB and 75.37dB at 2GHz frequency 1.6Vpp input. The −3dB bandwidth of the front-end circuit achieves 4.4GHz.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116708870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Low-Power Dual-Core Motion Estimation Chip Design and Validation for a Wireless Panoramic Endoscopy 无线全景内窥镜低功耗双核运动估计芯片设计与验证
2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181808
J. Zeng, Tsung-Yi Wu, Don-Gey Liu, Ching-Hwa Cheng
{"title":"A Low-Power Dual-Core Motion Estimation Chip Design and Validation for a Wireless Panoramic Endoscopy","authors":"J. Zeng, Tsung-Yi Wu, Don-Gey Liu, Ching-Hwa Cheng","doi":"10.1109/ISCAS46773.2023.10181808","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10181808","url":null,"abstract":"A low-power motion estimation chip is designed for a wireless panoramic endoscope system. This chip consists of two motion estimation cores and is implemented by a dual-Vdd low-power technique. The proposed technique is efficient in decreasing power consumption without reducing the operation frequency of the chip. From the full-function chip measurements, this dual-Vdd chip can reduce power consumption by 20%∼40% than the operation in single-Vdd at different clock frequencies.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116759341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A BJT-based SAR Temperature Sensor with a $5.12 text{pJ}cdot mathrm{K}^{2}$ Resolution FoM from −40 °C to 125 °C 基于bjt的SAR温度传感器，分辨率为$5.12 text{pJ}cdot mathm {K}^{2}$，范围为−40°C至125°C
2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181889
Fuyue Qian, Xiaowei Zhang, Yanye Chen, Jianxiong Xi, Qinwei Zhu, Lenian He
{"title":"A BJT-based SAR Temperature Sensor with a $5.12 text{pJ}cdot mathrm{K}^{2}$ Resolution FoM from −40 °C to 125 °C","authors":"Fuyue Qian, Xiaowei Zhang, Yanye Chen, Jianxiong Xi, Qinwei Zhu, Lenian He","doi":"10.1109/ISCAS46773.2023.10181889","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10181889","url":null,"abstract":"This paper proposes a BJT-based temperature sensor with a 16-bit SAR ADC fabricated in a standard 55-nm CMOS process. Errors resulting from the front end are reduced by using chopping, dynamic element matching, and PTAT circuit compensation. It obtains a resolution of 0.04 °C and a resolution figure of merit (FoM) of $5.12 text{pJ}cdot mathrm{K}^{2}$ with the utilization of a 16-bit SAR ADC. The sensor takes 0.1 ms to complete a round of conversion. The switched-capacitor amplifier is applied to scale up the input range of the SAR ADC and improve the effective dynamic range. The sensor achieves an accuracy of ± 0.6 °C from −40 °C to 125 °C. It occupies an area of 0.234 mm2 and draws a current of $6.4 mumathrm{A}$ (analog front end) from a 1.2-V supply voltage.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114262011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Live and low energy VVC Video Decoding powered by the OpenVVC Decoder on ARM Platform 实时和低能耗的VVC视频解码由ARM平台上的OpenVVC解码器提供支持
2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181412
Ibrahim Farhat, Pierre-Loup Cabarat, W. Hamidouche, Patrice Angot, Philipe Gonon, D. Ménard
{"title":"Live and low energy VVC Video Decoding powered by the OpenVVC Decoder on ARM Platform","authors":"Ibrahim Farhat, Pierre-Loup Cabarat, W. Hamidouche, Patrice Angot, Philipe Gonon, D. Ménard","doi":"10.1109/ISCAS46773.2023.10181412","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10181412","url":null,"abstract":"This demonstration showcases the potential of open-source software implementation for the new versatile video coding (VVC) standard, OpenVVC. The most complex VVC tools were optimized for ARM-type architectures using data parallelism through SIMD instructions. The demonstration has been tested on the NVIDIA Jetson AGX Xavier and on a NVIDIA SHIELD Android TV which showcased real-time decoding for FHD and HD video resolutions. By combining extensive data level parallelism with frame level parallelism, OpenVVC is able to maintain a remarkably low memory and energy consumption while achieving real-time decoding of videos with high resolution. These features present a great advantage for its integration on embedded devices with low computing and memory resources.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125324151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design Limitations in Oxide-Based Memristive Ternary Content Addressable Memories 基于氧化物的记忆型三元内容可寻址存储器的设计限制
2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181488
Leon Brackmann, Tobias Ziegler, A. Jafari, D. Wouters, M. Tahoori, S. Menzel
{"title":"Design Limitations in Oxide-Based Memristive Ternary Content Addressable Memories","authors":"Leon Brackmann, Tobias Ziegler, A. Jafari, D. Wouters, M. Tahoori, S. Menzel","doi":"10.1109/ISCAS46773.2023.10181488","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10181488","url":null,"abstract":"Memristive devices offer energy and area efficient non-volatile data storage for data-intense Ternary Content Ad-dressable Memory (TCAM) architectures. However, depending on the storage implementation in the bitcell design, the matching functionality shows multiple undesired discharge effects leading to false look-up results. In particular, the ternary storage suffers during the look-up operation from a poor resistance ratio, match-line leakage and device variabilities. In this paper, we investigate the inherent, design-dependent limitations in the ternary state storage capability due to different memristive TCAM bitcell design parameters and device variabilities. We test these limits based on variability-aware device simulations and isolate crucial parameters for the optimization of memristive TCAMs.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"1 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113973967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Two-step Linear-Exponential Incremental ADC with Slope Extended Counting 斜率扩展计数的两步线性指数增量ADC
2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10182190
Yuhan Pan, Qingxun Wang, Kaiquan Chen, Bin Cai, J. Qian, Yong Lian, Liang Qi
{"title":"A Two-step Linear-Exponential Incremental ADC with Slope Extended Counting","authors":"Yuhan Pan, Qingxun Wang, Kaiquan Chen, Bin Cai, J. Qian, Yong Lian, Liang Qi","doi":"10.1109/ISCAS46773.2023.10182190","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10182190","url":null,"abstract":"Two-step linear-exponential architectures can be applied to incremental ADCs (IADC) to achieve high resolution. In the first step, the ADC works as a normal first-order IADC while, in the second step, the exponential integrator is used to implement extended counting. There exist two architectures for the implementation of the exponential step, where the only difference depends on whether the input signal is connected or disconnected. By conducting a comparative analysis on such two slightly different linear-exponential architectures, we propose to combine the exponential and slope techniques to further boost the resolution without degrading its original thermal-noise suppression ability and DWA effectiveness. Mathematical analysis and simulation results are presented to confirm the principle of the proposed IADC.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122853237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Auto-LUT: Auto Approximation of Non-Linear Operations for Neural Networks on FPGA 基于FPGA的神经网络非线性运算的自动逼近
2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181655
Haodong Lu, Qichang Mei, Kun Wang
{"title":"Auto-LUT: Auto Approximation of Non-Linear Operations for Neural Networks on FPGA","authors":"Haodong Lu, Qichang Mei, Kun Wang","doi":"10.1109/ISCAS46773.2023.10181655","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10181655","url":null,"abstract":"The approximation of non-linear operation can simplify the logic design and save the system resources during the neural network inference on Field-Programmable Gate Array (FPGA). Prior work can approximate the non-linear operations with piecewise linear (PWL) function, but such approximation neglects considering the hardware overhead simultaneously. This paper proposes a novel approximation framework called Auto-LUT, which leverages a neural network to automatically approximate the non-linear operations. The framework formulates the approximation error and hardware overhead as a multi-objective optimization problem and employs an automated search mechanism to find the minimum number of segments and data bit width. To improve the approximation accuracy, we propose a bias clipping operation during the training of approximation networks, which enforces the model to approximate within the range of interest. Moreover, a hardware-friendly quantization scheme is further introduced to simulate the hardware behavior, thereby reducing the hardware overhead. Finally, a customized hardware architecture based on FPGA is utilized to deploy the quantized result. The experimental results show that Auto-LUT costs 56.32% less LUTs and 32.31% less flip-flops (FF) while reducing 4.32% approximation error compared to the state-of-the-art method.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123073595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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