A Metastability Inference and Avoidance Technique for Near-Threshold-Voltage Network-on-Chip

Abstract

With the application of low-power design technologies such as dynamic voltage and frequency scaling (DVFS) and globally asynchronous locally synchronization (GALS), a multi-voltage-/frequency-domain network-on-chip (NoC) suffers more and more serious metastability issue in inter-core data communication. To mitigate the metastability during the clock-domain crossing, a technique titled metastability inference and avoidance (MIAA) is presented. MIAA infers the potential metastability risk of a synchronizer's sampling clock through phase detection of a phase-related clock. MIAA avoids the occurrence of metastability by adaptively modulating the clock phase of the sampling clock once it infers the potential metastability risk. We designed a MIAA-based 40nm GALS $2\times 2$ NoC that contains four independent voltage/frequency domains. The post-layout simulation results show that MIAA can well predict the metastability risks and reduce the probability of metastability to zero across a wide range of frequency ratios. The metastability mitigation allows us to use a single flip-flop instead of a multi-stage synchronizer for synchronization in the NoC, thereby improving the latency and throughput of the NoC by 40.2% and 79%, respectively.