2023 IEEE International Symposium on Circuits and Systems (ISCAS)最新文献_第4页

A Fully Integrated dToF System-on-Chip with High Precision Using Adaptive Optical Power Control and Shifted Histogram-Bin Binning 采用自适应光功率控制和移位直方图- bin bin的高精度全集成dof片上系统

2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181483

Hengwei Yu, Shenglong Zhuo, Yifan Wu, Long Wang, Jiqing Xu, Jier Wang, Zhihong Lin, Patrick Chiang

引用次数: 0

An 800G Integrated Silicon-Photonic Transmitter based on 16-Channel Mach-Zehnder Modulator and Co-Designed 5.35pJ/bit CMOS Drivers 基于16通道Mach-Zehnder调制器和5.35pJ/bit CMOS驱动器的800G集成硅光子发射机

2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181563

Jingbo Shi, Han Liu, Tao Yang, Ming Jin, Haowen Shu, Fenghe Yang, Lei Shi, Yuansheng Tao, Jianrui Deng, Ruixuan Chen, Chan-Chung Han, Jian Liu, N. Wu, Nan Qi, Liyuan Liu

{"title":"An 800G Integrated Silicon-Photonic Transmitter based on 16-Channel Mach-Zehnder Modulator and Co-Designed 5.35pJ/bit CMOS Drivers","authors":"Jingbo Shi, Han Liu, Tao Yang, Ming Jin, Haowen Shu, Fenghe Yang, Lei Shi, Yuansheng Tao, Jianrui Deng, Ruixuan Chen, Chan-Chung Han, Jian Liu, N. Wu, Nan Qi, Liyuan Liu","doi":"10.1109/ISCAS46773.2023.10181563","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10181563","url":null,"abstract":"A 800G integrated silicon-photonic transmitter is presented, including a 16-channel photonic integrated chip (PIC) and two electrical chiplets (EICs) that are realized based on an arrayed travelling wave dual-drive Mach-Zehnder modulator (MZM) and two 8-channel CMOS drivers. The proposed multi-channel PIC is fabricated on a high-resistance silicon-on-insulator (SOI) wafer with a 220 nm thick silicon layer and a $mathbf{2} boldsymbol{mu} mathbf{m}$ thick buried oxide (BOX) using the foundry-ready CMOS process, while the drivers are implemented in a standard $mathbf{65}mathbf{nm}$ CMOS process. The driver employs a combination of distributed architecture, 2-tap feedforward equalization (FFE) and push-pull output stage, experimentally exhibiting an averaged bandwidth higher than 28.5GHz and a differential swing of 4.0Vpp on $mathbf{50}mathbf{Omega}$ load, respectively. The 50Gb/s electrical eye-diagram is measured with 1.41ps rms-jitter, while the optical extinction ratio (ER) exceeds 3.0dB with 5.35pJ/bit power efficiency.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121545545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Power Side-Channel Attack on Flash ADC 对Flash ADC的功率侧信道攻击

2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181331

Ziyi Chen, I. Savidis

{"title":"A Power Side-Channel Attack on Flash ADC","authors":"Ziyi Chen, I. Savidis","doi":"10.1109/ISCAS46773.2023.10181331","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10181331","url":null,"abstract":"In this paper, a monotonic power side-channel attack (PSA) is proposed to analyze the security vulnerabilities of flash analog-to-digital converters (ADC), where the digital output of a flash ADC is determined by characterizing the monotonic relationship between the traces of the power consumed and the applied input signals. A novel technique that leverages clock phase division is proposed to secure the power side channel information of a 4-bit flash ADC. The proposed technique adds randomness to decorrelate the input signal from the given power trace as the execution phase of each comparator depends on a thermometer code computed from the previous seven clock cycles. The monotonic PSA is executed on both a secured and unsecured ADC, with results indicating 1.9 bits of information leakage from an unprotected ADC and no data leakage from a protected ADC as the bit-wise accuracy is approximately 50% when secured. The monotonic PSA is more effective at attacking a flash ADC architecture than either a convolutional neural network based PSA or a correlation template PSA. The secured ADC core occupies approximately 2% more area than a non-secure ADC in a 65 nm process, and provides a sampling frequency of up to 500 MHz at a supply voltage of 1.2 V.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121701554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Efficient Implementation of Activation Function on FPGA for Accelerating Neural Networks 加速神经网络激活函数在FPGA上的高效实现

2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181406

Kai Qian, Yinqiu Liu, Zexu Zhang, Kun Wang

引用次数: 0

A 50-MHz Bandwidth and 50.6-dBm OOB-IIP3 Transimpedance Amplifier Based on a Three-Stage Pseudo-Differential OTA 基于三级伪差分OTA的50 mhz带宽50.6 dbm OOB-IIP3跨阻放大器

2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181693

Cong Tao, Liangbo Lei, Zhiliang Hong, Yumei Huang

{"title":"A 50-MHz Bandwidth and 50.6-dBm OOB-IIP3 Transimpedance Amplifier Based on a Three-Stage Pseudo-Differential OTA","authors":"Cong Tao, Liangbo Lei, Zhiliang Hong, Yumei Huang","doi":"10.1109/ISCAS46773.2023.10181693","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10181693","url":null,"abstract":"A 50 MHz bandwidth (BW) transimpedance ampli-fier (TIA) is designed for 5G Sub-6GHz SAW-less current-mode receivers (RX). It's based on an operational transconductance amplifier (OTA). To tolerate blockers, the TIA must exhibit excellent in-band (IB) and out-of-band (OOB) linearity, which in turn requires OTAs with high BW and gain. Traditional two-stage OTAs struggle to achieve this under low power consumption (PC), so this paper employs a three-stage OTA. A pseudo-differential structure without the tail current source is used to accommodate low supply voltages (Vdd). Differential-mode (DM) stability relies on feedforward (FF) compensation within the OTA and zero compensation in the feedback network. Common mode (CM) is stabilized by five different common mode rejection (CMR) techniques. The circuit is designed and simulated in a 40 nm low power (LP) CMOS technology with a Vdd of 1.2V. The post-layout simulation results show that when IM3 is set to 30 MHz, the TIA's IB and OOB IIP3 reach 31.6 dBm and 50.6 dBm, respectively. The minimum input-referred noise (IRN) is 5.14 $mathbf{nV}/sqrt{Hz}$. The corresponding FoM value is as high as 186.3 dBJ-1, exceeding all previous designs. The chip consumes 10.4 mW of power and occupies only 0.016mm2.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"533 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124513747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Reduced Precision Redundancy Systems by Approximation (RPA): Design and Analysis 基于近似的低精度冗余系统:设计与分析

2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181543

Salin Junsangsri, Fabrizio Lombardi

引用次数: 0

Design of Cryo-CMOS Analog Circuits using the $G_{m}/I_{D}$ Approach 使用$G_{m}/ $ I_{D}方法设计Cryo-CMOS模拟电路

2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181986

C. Enz, Hung-Chi Han

引用次数: 0

A Reconfigurable 1T1C eDRAM-based Spiking Neural Network Computing-In-Memory Processor for High System-Level Efficiency 高系统级效率的可重构1T1C edram脉冲神经网络内存计算处理器

2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181420

Seryeong Kim, Soyeon Kim, Soyeon Um, Sangjin Kim, Zhiyong Li, Sanyeob Kim, Wooyoung Jo, H.-J. Yoo

引用次数: 0

Deep Sparse Depth Completion Using Joint Depth and Normal Estimation 基于联合深度和正态估计的深度稀疏补全

2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181618

Ying Li, Cheolkon Jung

{"title":"Deep Sparse Depth Completion Using Joint Depth and Normal Estimation","authors":"Ying Li, Cheolkon Jung","doi":"10.1109/ISCAS46773.2023.10181618","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10181618","url":null,"abstract":"Depth completion densifies sparse depth images obtained from LiDAR and is a great challenge due to the given extremely sparse information. In this paper, we propose deep sparse depth completion using joint depth and normal estimation. There exists a mutually convertible geometric relationship between depth and surface normal in 3D coordinate space. Based on the geometric relationship, we build a novel adversarial model that consists of one generator and two discriminators. We adopt an encoder-decoder structure for the generator. The encoder extracts features from RGB image, sparse depth image and its binary mask that represent the inherent geometric relationship between depth and surface normal, while two decoders with the same structure generate dense depth and surface normal based on the geometric relationship. We utilize two discriminators to generate guide information for sparse depth completion from the input RGB image while imposing an auxiliary geometric constraint for depth refinement. Experimental results on KITTI dataset show that the proposed method generates dense depth images with accurate object boundaries and outperforms state-of-the-art ones in terms of visual quality and quantitative measurements.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126537895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Theoretical Analysis of Bidirectional Bifurcation Phenomena in DC Cascaded Converter Systems 直流级联变换器系统中双向分岔现象的理论分析

2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181499

Li Ding, C. Tse

引用次数: 0