Jingbo Shi, Han Liu, Tao Yang, Ming Jin, Haowen Shu, Fenghe Yang, Lei Shi, Yuansheng Tao, Jianrui Deng, Ruixuan Chen, Chan-Chung Han, Jian Liu, N. Wu, Nan Qi, Liyuan Liu
{"title":"基于16通道Mach-Zehnder调制器和5.35pJ/bit CMOS驱动器的800G集成硅光子发射机","authors":"Jingbo Shi, Han Liu, Tao Yang, Ming Jin, Haowen Shu, Fenghe Yang, Lei Shi, Yuansheng Tao, Jianrui Deng, Ruixuan Chen, Chan-Chung Han, Jian Liu, N. Wu, Nan Qi, Liyuan Liu","doi":"10.1109/ISCAS46773.2023.10181563","DOIUrl":null,"url":null,"abstract":"A 800G integrated silicon-photonic transmitter is presented, including a 16-channel photonic integrated chip (PIC) and two electrical chiplets (EICs) that are realized based on an arrayed travelling wave dual-drive Mach-Zehnder modulator (MZM) and two 8-channel CMOS drivers. The proposed multi-channel PIC is fabricated on a high-resistance silicon-on-insulator (SOI) wafer with a 220 nm thick silicon layer and a $\\mathbf{2}\\ \\boldsymbol{\\mu} \\mathbf{m}$ thick buried oxide (BOX) using the foundry-ready CMOS process, while the drivers are implemented in a standard $\\mathbf{65}\\mathbf{nm}$ CMOS process. The driver employs a combination of distributed architecture, 2-tap feedforward equalization (FFE) and push-pull output stage, experimentally exhibiting an averaged bandwidth higher than 28.5GHz and a differential swing of 4.0Vpp on $\\mathbf{50}\\mathbf{\\Omega}$ load, respectively. The 50Gb/s electrical eye-diagram is measured with 1.41ps rms-jitter, while the optical extinction ratio (ER) exceeds 3.0dB with 5.35pJ/bit power efficiency.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An 800G Integrated Silicon-Photonic Transmitter based on 16-Channel Mach-Zehnder Modulator and Co-Designed 5.35pJ/bit CMOS Drivers\",\"authors\":\"Jingbo Shi, Han Liu, Tao Yang, Ming Jin, Haowen Shu, Fenghe Yang, Lei Shi, Yuansheng Tao, Jianrui Deng, Ruixuan Chen, Chan-Chung Han, Jian Liu, N. Wu, Nan Qi, Liyuan Liu\",\"doi\":\"10.1109/ISCAS46773.2023.10181563\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 800G integrated silicon-photonic transmitter is presented, including a 16-channel photonic integrated chip (PIC) and two electrical chiplets (EICs) that are realized based on an arrayed travelling wave dual-drive Mach-Zehnder modulator (MZM) and two 8-channel CMOS drivers. The proposed multi-channel PIC is fabricated on a high-resistance silicon-on-insulator (SOI) wafer with a 220 nm thick silicon layer and a $\\\\mathbf{2}\\\\ \\\\boldsymbol{\\\\mu} \\\\mathbf{m}$ thick buried oxide (BOX) using the foundry-ready CMOS process, while the drivers are implemented in a standard $\\\\mathbf{65}\\\\mathbf{nm}$ CMOS process. The driver employs a combination of distributed architecture, 2-tap feedforward equalization (FFE) and push-pull output stage, experimentally exhibiting an averaged bandwidth higher than 28.5GHz and a differential swing of 4.0Vpp on $\\\\mathbf{50}\\\\mathbf{\\\\Omega}$ load, respectively. The 50Gb/s electrical eye-diagram is measured with 1.41ps rms-jitter, while the optical extinction ratio (ER) exceeds 3.0dB with 5.35pJ/bit power efficiency.\",\"PeriodicalId\":177320,\"journal\":{\"name\":\"2023 IEEE International Symposium on Circuits and Systems (ISCAS)\",\"volume\":\"38 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-05-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2023 IEEE International Symposium on Circuits and Systems (ISCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCAS46773.2023.10181563\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS46773.2023.10181563","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An 800G Integrated Silicon-Photonic Transmitter based on 16-Channel Mach-Zehnder Modulator and Co-Designed 5.35pJ/bit CMOS Drivers
A 800G integrated silicon-photonic transmitter is presented, including a 16-channel photonic integrated chip (PIC) and two electrical chiplets (EICs) that are realized based on an arrayed travelling wave dual-drive Mach-Zehnder modulator (MZM) and two 8-channel CMOS drivers. The proposed multi-channel PIC is fabricated on a high-resistance silicon-on-insulator (SOI) wafer with a 220 nm thick silicon layer and a $\mathbf{2}\ \boldsymbol{\mu} \mathbf{m}$ thick buried oxide (BOX) using the foundry-ready CMOS process, while the drivers are implemented in a standard $\mathbf{65}\mathbf{nm}$ CMOS process. The driver employs a combination of distributed architecture, 2-tap feedforward equalization (FFE) and push-pull output stage, experimentally exhibiting an averaged bandwidth higher than 28.5GHz and a differential swing of 4.0Vpp on $\mathbf{50}\mathbf{\Omega}$ load, respectively. The 50Gb/s electrical eye-diagram is measured with 1.41ps rms-jitter, while the optical extinction ratio (ER) exceeds 3.0dB with 5.35pJ/bit power efficiency.
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