2023 IEEE International Symposium on Circuits and Systems (ISCAS)最新文献_第5页

SSCAE: A Neuromorphic SNN Autoencoder for sc-RNA-seq Dimensionality Reduction SSCAE:用于sc- rna序列降维的神经形态SNN自编码器

2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181994

Tim Zhang, A. Amirsoleimani, J. Eshraghian, M. Azghadi, R. Genov, Yu Xia

引用次数: 1

A 0.98 pJ/Cycle 3.7 ppm Long-Term Stability Frequency-Locked Oscillator with Switched-Capacitor and Switched-Resistor Techniques 采用开关电容和开关电阻技术的0.98 pJ/Cycle 3.7 ppm长期稳定锁频振荡器

2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10182024

Yun-Sheng Hsieh, Bo Li, Kuang-Wei Cheng

引用次数: 0

IVATS: A Leakage Reduction Technique Based on Input Vector Analysis and Transistor Stacking in CMOS Circuits IVATS:一种基于输入矢量分析和晶体管堆叠的CMOS电路漏损降低技术

2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10182138

Lishuo Deng, Keran Li, Weiwei Shan

{"title":"IVATS: A Leakage Reduction Technique Based on Input Vector Analysis and Transistor Stacking in CMOS Circuits","authors":"Lishuo Deng, Keran Li, Weiwei Shan","doi":"10.1109/ISCAS46773.2023.10182138","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10182138","url":null,"abstract":"Leakage reduction is crucial for always-on IoT applications in which static power consumption of the memory cells accounts for a large proportion of the total power. Even with high threshold voltage transistors, the leakage is still considerable. This paper proposes a novel technique based on input vector analysis and transistor stacking to analyze and suppress leakage, especially for extremely high threshold voltage (EHVT) circuits operating in the near/sub-threshold regime. At the device level, we consider the leakage ratio of each transistor terminal, which improves the universality of the method. At the circuit level, we innovatively propose the concepts of critical leakage path, leakage power components, and public leakage path to help designers locate the sources of leakage more precisely. We apply the method to a 28nm-EHVT low leakage tristate latch-like memory cell in a serial Fast Fourier Transform (FFT) circuit and find that inserting one stacking NMOS and using “01” stack to reduce the substrate leakage of PMOS can effectively suppress leakage. The average leakage power consumption of the optimized cell is reduced by 42% in the pre-layout simulation. A 26.87% and 17.52% leakage power reduction in the custom cell and the serial FFT circuit is achieved after the layout design and the synthesis.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132252405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Fast VVC Intra Encoding for Video Coding for Machines 用于机器视频编码的快速VVC内编码

2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181507

Aorui Gou, Heming Sun, Xiaoyang Zeng, Yibo Fan

{"title":"Fast VVC Intra Encoding for Video Coding for Machines","authors":"Aorui Gou, Heming Sun, Xiaoyang Zeng, Yibo Fan","doi":"10.1109/ISCAS46773.2023.10181507","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10181507","url":null,"abstract":"Traditional video coding technologies compress and reconstruct the video frames, which focus on human perception. However, video coding for machines (VCM) uses the feature stream to bridge the correlation between human perception and machine intelligence for vision tasks. We extract the features for the CU with different shapes with part of resnet architecture for VCM. However, the feature-based methods use the model to complete the forward process, which is very time-consuming for its complex architecture and parameter size. The CU architecture for the feature extraction further increases the operation times. A fast algorithm based on the Histogram of oriented gradient (H OG) is proposed for the video coding for machines with VVC intra to overcome the time-consuming problems while maintaining the performance for the vision tasks with codec. The correlation of the mode decision with the VCM performance is discussed to motivate the fast intra coding for V CM. Moreover, the VTM and VVenc are used to verify the universality of the proposed method. The proposed methods can speed up the fast encoding for 35.21 % time saving with 0.26 increment for AP50 for the cityscapes dataset compared with the VTM10.0.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"15 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132335912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Security Scalability of Arbiter PUF Designs 仲裁者PUF设计的安全可扩展性

2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181541

Sara Alahmadi, Haytham Idriss, P. Rojas, M. Bayoumi

{"title":"Security Scalability of Arbiter PUF Designs","authors":"Sara Alahmadi, Haytham Idriss, P. Rojas, M. Bayoumi","doi":"10.1109/ISCAS46773.2023.10181541","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10181541","url":null,"abstract":"Physically Unclonable Functions (PUFs) are hardware security primitives that can offer an alternative lightweight security solution for authenticating constrained Internet of Things (IoT) devices. However, PUFs are susceptible to modeling attacks, requiring the adoption of various design approaches to increase their resiliency. Many research efforts propose design approaches that offer better security against modeling attacks. This work investigates state-of-the-art modeling attacks performed on well-known Arbiter-based PUF architectures highlighting the best-fit modeling algorithm for different design approaches. Furthermore, the area efficiency of studied PUF designs is examined, and the optimal PUF design approaches for various area constraints are suggested. Such an assessment is required to evaluate PUF security accurately and guide the PUF community toward better practices. The findings revealed that some machine-learning algorithms performed better on a particular design. Additionally, when considering area overhead, we found that some PUF designs offer less security per area unit than their simpler counterparts. Accordingly, certain design elements are more efficient and add more security.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130123557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Efficient Frequency Domain Vision Pipeline From RAW Images to Backend Tasks 从原始图像到后端任务的高效频域视觉管道

2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10182018

Hao Li, Weiti Zhou, Xiangyu Zhang, Xin Lou

引用次数: 0

Concealable Physically Unclonable Functions and Key Generation Using a Geiger Mode Imager 使用盖革模式成像仪可隐藏的物理不可克隆函数和密钥生成

2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10182123

Md. Sakibur Rahman Sajal, M. Dandin

{"title":"Concealable Physically Unclonable Functions and Key Generation Using a Geiger Mode Imager","authors":"Md. Sakibur Rahman Sajal, M. Dandin","doi":"10.1109/ISCAS46773.2023.10182123","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10182123","url":null,"abstract":"We report a novel hardware method for generating authentication keys based on a physically unclonable function (PUF) of a perimeter-gated single photon avalanche diode (pg-SPAD) imager. We tested three $64times 64$ pg-SPAD imagers over a temperature range extending from 27°C to 75°C and demonstrated that authentication keys can be generated with quantifiable difference and that they are resilient to temperature change. We used the imager's spatial dark count variation as a PUF, i.e., as a means to generate unique hardware fingerprints on which the keys are based. Without applying complex key generation algorithms or temperature compensation techniques, we obtained approximately 0.1 in average normalized Hamming distance (nHD) between intra-chip keys generated from the same challenge and approximately 0.5 in average nHD between intra-chip keys generated from different challenges. Inter-chip keys generated with the same challenge also showed sufficient differentiation, i.e., a nHD of approximately 0.5. Additionally, we demonstrate that perimeter gating offers an additional security feature as it can either alter or obfuscate the imager's PUF.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134152943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Live Demonstration: A Low-Power Dual-Core Motion Estimation Chip Design and Validation for a Wireless Panoramic Endoscopy 现场演示:用于无线全景内窥镜的低功耗双核运动估计芯片设计与验证

2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181322

J. Zeng, Tsung-Yi Wu, Don-Gey Liu, Ching-Hwa Cheng

引用次数: 0

FPCIM: A Fully-Parallel Robust ReRAM CIM Processor for Edge AI Devices FPCIM:用于边缘人工智能设备的全并行鲁棒ReRAM CIM处理器

2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181402

Yan-Cheng Guo, Wei-Tien Lin, T. Hou, Tian-Sheuan Chang

引用次数: 0

An Open Source Compatible Framework to Fully Autonomous Digital LDO Generation 一个完全自主数字LDO生成的开源兼容框架

2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181884

Yaswanth K. Cherivirala, Mehdi Saligane, D. Wentzloff

{"title":"An Open Source Compatible Framework to Fully Autonomous Digital LDO Generation","authors":"Yaswanth K. Cherivirala, Mehdi Saligane, D. Wentzloff","doi":"10.1109/ISCAS46773.2023.10181884","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10181884","url":null,"abstract":"This work presents an open-source methodology to automate the design and layout of a low dropout (LDO) regulator from high-level performance specifications. LDO designs with this methodology have been demonstrated in commercial 65nm, 12nm, 130nm processes and the open-source 130nm Skywater PDK. The tool currently supports LDO designs with 50mV/100mV dropout for an input voltage range of 0.6V-1.3V (130nm and 65nm), 0.6V-0.9V (12nm), 1.8V-3.3V (Skywater 130nm) and a maximum load current ranging from 0.5mA-25mA (130nm and 65nm), 1mA-20mA (12nm), 0.5mA-50mA (Skywater 130nm). Cell-based design approach is adopted using an auxiliary cell library to enable mixed-signal design synthesis. A port to a new technology only requires a one-time manual layout for auxiliary library generation. The design automation includes a technology-agnostic modeling step and generates the LDO layout automatically. A bi-directional shift register based DLDO with a 1-bit comparator and a stochastic flash ADC (achieving 15x faster settling time) for error detection has been generated using the tool and validated using silicon measurements from 65nm process. LDO designs with different switch types and load configurations have been fabricated in open-source Skywater 130nm.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131590176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3