2023 IEEE International Symposium on Circuits and Systems (ISCAS)最新文献_第6页

Virtual-Sensing for Active Noise Control Using Reflected Waves 利用反射波进行主动噪声控制的虚拟传感

2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10182140

Itsuki Kojima, Hajime Kobayashi, N. Sasaoka

引用次数: 0

SS-AXI: Secure and Safe Access Control Mechanism for Multi-Tenant Cloud FPGAs SS-AXI:多租户云fpga的安全访问控制机制

2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181609

Emre Karabulut, Amro Awad, Aydin Aysu

{"title":"SS-AXI: Secure and Safe Access Control Mechanism for Multi-Tenant Cloud FPGAs","authors":"Emre Karabulut, Amro Awad, Aydin Aysu","doi":"10.1109/ISCAS46773.2023.10181609","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10181609","url":null,"abstract":"FPGAs are newly added to the cloud to offer energy-efficient acceleration. Multi-tenancy is an emerging phenomenon in cloud FPGAs to enable resource efficiency. In a multi-tenant scenario, multiple users can share the same FPGA fabric either spatially (i.e., tenants share different resources at the same time) or temporally (tenants share the same resources in different time slots). Undesired access or manipulation of other tenant's data can cause security and safety issues. Although safety/security concepts in access control policies have been thoroughly studied in conventional cloud systems, they are relatively unknown for cloud FPGAs. Moreover, these concepts may not trivially extend to cloud FPGAs due to their different nature. This paper proposes an improved access control mechanism for multi-tenant cloud FPGAs. Compared to existing commercial tools, our solution allows dynamic configuration of access control privileges. Compared to earlier academic proposals with dynamic configuration, the results show that our proposal has three advantages: (i) enabling secure resource sharing of on-chip BRAMs to tenants, (ii) enabling safe sharing by resolving deadlocks and faulty access requests, and (iii) improvement in latency and throughput.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130868244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

YARB: a Methodology to Characterize Regular Expression Matching on Heterogeneous Systems 异构系统中正则表达式匹配的一种表征方法

2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181547

F. Carloni, Davide Conficconi, Ilaria Moschetto, M. Santambrogio

引用次数: 1

A Low-Distortion Current-Mode Signal Generator for Wide-Range Bioimpedance Spectroscopy 用于宽范围生物阻抗谱的低失真电流模式信号发生器

2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181880

A. F. Schrunder, A. Rusu

引用次数: 0

Energy-Efficient Short-Time Fourier Transform for Partial Window Overlapping 部分窗口重叠的节能短时傅里叶变换

2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181940

Charalampos Eleftheriadis, M. Garrido, G. Karakonstantis

引用次数: 0

Modeling Retention Errors on Modern 3D-Flash Products 现代3D-Flash产品的建模保留错误

2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181929

Jianwei Liao, Jiewen Tang, Jun Li, Junhao Luo, Chenqi Xiao, Zhigang Cai, Lei Chen

{"title":"Modeling Retention Errors on Modern 3D-Flash Products","authors":"Jianwei Liao, Jiewen Tang, Jun Li, Junhao Luo, Chenqi Xiao, Zhigang Cai, Lei Chen","doi":"10.1109/ISCAS46773.2023.10181929","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10181929","url":null,"abstract":"The innovative stacking architecture of 3D NAND flash offers a promising solution to increase the capacity of flash memory and further cut down the per-unit price. Such compact architectures, however, cause varied kinds of errors because of the hardware nature. Specially, retention errors are primary causes of read retries in high-density flash memory, which are induced by charge leakage over time. This paper proposes an empirical mathematical model to estimate the error rate caused by retention errors on the granularity of block, which is the basic program/erase (P/E) unit in 3D NAND flash memory. Specifically, we build the generalized model by considering the factors of layer-to-layer interference, early retention loss, the P/E cycle and the retention time of data of 3D NAND flash memory. Then, we validate the model on four commercial 3D NAND flash products, and the experimental results verify the accuracy of our proposed estimation model. At last, we apply our model in the existing I/O optimization of write scheduling for 3D NAND flash memory, for showing its contributions to better I/O performance.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132669437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Macro Construction Rules and Optimization for Long Bit Parallel Prefix Adders 长位并行前缀加法器的宏构造规则及优化

2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10182180

M. Kaneko

引用次数: 0

A Scalable Annealing Processing Architecture for Fully-Connected Ising Models 全连通Ising模型的可扩展退火处理体系

2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181623

Dong Jiang, Xiangrui Wang, Zhanhong Huang, Yukang Huang, Enyi Yao

引用次数: 0

A/D Alleviator: Reducing Analog-to-Digital Conversions in Compute-In-Memory with Augmented Analog Accumulation A/D缓解:通过增强模拟积累减少内存计算中的模数转换

2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181895

Weidong Cao, Xuan Zhang

引用次数: 0

Neural network scoring for efficient computing 神经网络评分的高效计算

2023 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2023-05-21 DOI: 10.1109/ISCAS46773.2023.10181766

Hugo Waltsburger, Erwan Libessart, Chengfang Ren, A. Kolar, R. Guinvarc’h

{"title":"Neural network scoring for efficient computing","authors":"Hugo Waltsburger, Erwan Libessart, Chengfang Ren, A. Kolar, R. Guinvarc’h","doi":"10.1109/ISCAS46773.2023.10181766","DOIUrl":"https://doi.org/10.1109/ISCAS46773.2023.10181766","url":null,"abstract":"Much work has been dedicated to estimating and optimizing workloads in high-performance computing (HPC) and deep learning. However, researchers have typically relied on few metrics to assess the efficiency of those techniques. Most notably, the accuracy, the loss of the prediction, and the computational time with regard to GPUs or/and CPUs characteristics. It is rare to see figures for power consumption, partly due to the difficulty of obtaining accurate power readings. In this paper, we introduce a composite score that aims to characterize the trade-off between accuracy and power consumption measured during the inference of neural networks. For this purpose, we present a new open-source tool allowing researchers to consider more metrics: granular power consumption, but also RAM/CPU/GPU utilization, as well as storage, and network input/output (I/O). To our best knowledge, it is the first fit test for neural architectures on hardware architectures. This is made possible thanks to reproducible power efficiency measurements. We applied this procedure to state-of-the-art neural network architectures on miscellaneous hardware. One of the main applications and novelties is the measurement of algorithmic power efficiency. The objective is to allow researchers to grasp their algorithms' efficiencies better. This methodology was developed to explore trade-offs between energy usage and accuracy in neural networks. It is also useful when fitting hardware for a specific task or to compare two architectures more accurately, with architecture exploration in mind.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114697547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0