Modeling Retention Errors on Modern 3D-Flash Products

The innovative stacking architecture of 3D NAND flash offers a promising solution to increase the capacity of flash memory and further cut down the per-unit price. Such compact architectures, however, cause varied kinds of errors because of the hardware nature. Specially, retention errors are primary causes of read retries in high-density flash memory, which are induced by charge leakage over time. This paper proposes an empirical mathematical model to estimate the error rate caused by retention errors on the granularity of block, which is the basic program/erase (P/E) unit in 3D NAND flash memory. Specifically, we build the generalized model by considering the factors of layer-to-layer interference, early retention loss, the P/E cycle and the retention time of data of 3D NAND flash memory. Then, we validate the model on four commercial 3D NAND flash products, and the experimental results verify the accuracy of our proposed estimation model. At last, we apply our model in the existing I/O optimization of write scheduling for 3D NAND flash memory, for showing its contributions to better I/O performance.