Macro Construction Rules and Optimization for Long Bit Parallel Prefix Adders

Abstract

In the optimization of long bit-length adder design, the maintenance of solution space for adder structures and the control of wire length are important keys. This paper focuses on parallel prefix adders, and proposes macro construction rules based on the procedural construction framework for parallel prefix adders, and specification of application sequence using binary tree labeling. In addition, bit-line shuffling is combined in the design optimization for further improvement of delay performance. Proposed co-optimization of logical structure and bit-line placement improves the maximum path delay by 7% compared with the best one among the well-known benchmark parallel prefix adders. The improvement seems not to be significant, but the proposed method can easily be applied to variety of designs with different objectives, different parameter settings, etc.