IVATS: A Leakage Reduction Technique Based on Input Vector Analysis and Transistor Stacking in CMOS Circuits

Abstract

Leakage reduction is crucial for always-on IoT applications in which static power consumption of the memory cells accounts for a large proportion of the total power. Even with high threshold voltage transistors, the leakage is still considerable. This paper proposes a novel technique based on input vector analysis and transistor stacking to analyze and suppress leakage, especially for extremely high threshold voltage (EHVT) circuits operating in the near/sub-threshold regime. At the device level, we consider the leakage ratio of each transistor terminal, which improves the universality of the method. At the circuit level, we innovatively propose the concepts of critical leakage path, leakage power components, and public leakage path to help designers locate the sources of leakage more precisely. We apply the method to a 28nm-EHVT low leakage tristate latch-like memory cell in a serial Fast Fourier Transform (FFT) circuit and find that inserting one stacking NMOS and using “01” stack to reduce the substrate leakage of PMOS can effectively suppress leakage. The average leakage power consumption of the optimized cell is reduced by 42% in the pre-layout simulation. A 26.87% and 17.52% leakage power reduction in the custom cell and the serial FFT circuit is achieved after the layout design and the synthesis.