Yaswanth K. Cherivirala, Mehdi Saligane, D. Wentzloff
{"title":"An Open Source Compatible Framework to Fully Autonomous Digital LDO Generation","authors":"Yaswanth K. Cherivirala, Mehdi Saligane, D. Wentzloff","doi":"10.1109/ISCAS46773.2023.10181884","DOIUrl":null,"url":null,"abstract":"This work presents an open-source methodology to automate the design and layout of a low dropout (LDO) regulator from high-level performance specifications. LDO designs with this methodology have been demonstrated in commercial 65nm, 12nm, 130nm processes and the open-source 130nm Skywater PDK. The tool currently supports LDO designs with 50mV/100mV dropout for an input voltage range of 0.6V-1.3V (130nm and 65nm), 0.6V-0.9V (12nm), 1.8V-3.3V (Skywater 130nm) and a maximum load current ranging from 0.5mA-25mA (130nm and 65nm), 1mA-20mA (12nm), 0.5mA-50mA (Skywater 130nm). Cell-based design approach is adopted using an auxiliary cell library to enable mixed-signal design synthesis. A port to a new technology only requires a one-time manual layout for auxiliary library generation. The design automation includes a technology-agnostic modeling step and generates the LDO layout automatically. A bi-directional shift register based DLDO with a 1-bit comparator and a stochastic flash ADC (achieving 15x faster settling time) for error detection has been generated using the tool and validated using silicon measurements from 65nm process. LDO designs with different switch types and load configurations have been fabricated in open-source Skywater 130nm.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS46773.2023.10181884","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
This work presents an open-source methodology to automate the design and layout of a low dropout (LDO) regulator from high-level performance specifications. LDO designs with this methodology have been demonstrated in commercial 65nm, 12nm, 130nm processes and the open-source 130nm Skywater PDK. The tool currently supports LDO designs with 50mV/100mV dropout for an input voltage range of 0.6V-1.3V (130nm and 65nm), 0.6V-0.9V (12nm), 1.8V-3.3V (Skywater 130nm) and a maximum load current ranging from 0.5mA-25mA (130nm and 65nm), 1mA-20mA (12nm), 0.5mA-50mA (Skywater 130nm). Cell-based design approach is adopted using an auxiliary cell library to enable mixed-signal design synthesis. A port to a new technology only requires a one-time manual layout for auxiliary library generation. The design automation includes a technology-agnostic modeling step and generates the LDO layout automatically. A bi-directional shift register based DLDO with a 1-bit comparator and a stochastic flash ADC (achieving 15x faster settling time) for error detection has been generated using the tool and validated using silicon measurements from 65nm process. LDO designs with different switch types and load configurations have been fabricated in open-source Skywater 130nm.