2018 4th International Conference on Devices, Circuits and Systems (ICDCS)最新文献

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Investigation of Gate All Around Junctionless Nanowire Transistor with Arbitrary Polygonal Cross Section 任意多边形截面栅极无结纳米线晶体管的研究
2018 4th International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2018-03-01 DOI: 10.1109/ICDCSYST.2018.8605133
Monika Sharma, Mridula Gupta, R. Narang, M. Saxena
{"title":"Investigation of Gate All Around Junctionless Nanowire Transistor with Arbitrary Polygonal Cross Section","authors":"Monika Sharma, Mridula Gupta, R. Narang, M. Saxena","doi":"10.1109/ICDCSYST.2018.8605133","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605133","url":null,"abstract":"This paper presents an analytical model for the calculation of the potential distribution in junctionless nanowire transistors with an arbitrary regular polygon as a cross-section. Two different cases concerning circular and square cross-sections are particularly investigated and analyzed. Poisson’s equation is being solved and electric potential is obtained. With the potential model, an explicit comparison is done between square cross-section GAA transistor and cylindrical GAA transistor which is being further investigated for circuit design and tested for the CMOS inverter application. The proposed model is validated using 3D ATLAS simulations.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132485969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 3-Port Y-Junction Power Splitter for 60GHz Applications 用于60GHz应用的3端口y结功率分配器
2018 4th International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2018-03-01 DOI: 10.1109/ICDCSYST.2018.8605176
K. Kumar, T. Shanmuganantham
{"title":"A 3-Port Y-Junction Power Splitter for 60GHz Applications","authors":"K. Kumar, T. Shanmuganantham","doi":"10.1109/ICDCSYST.2018.8605176","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605176","url":null,"abstract":"In this research paper, Y-Junction power splitter is designed for 60GHz in the millimeter wave frequency range for upcoming new technologies in wireless and wire communications. Y-Junction power splitter is designed by using rectangular substrate integrated waveguide technology with grounded coplanar waveguide technique is used as transmission path. Rogers RT/Duriod 5880 Substrate material is used to design Y-Junction power splitter with loss tangent as 0.0009 and dielectric constant 2.2. This Y-Junction power splitter analyzed the characteristic like reflection coefficient, voltage standing wave ratio and electric fields. This Y-Junction power splitter gives max reflection coefficient of -50dB at 60.1GHz, voltage standing wave ratio of 1.02 and transmission coefficient as -3.39dB at 60GHz. This Y-Junction power splitter gives 2. 32GHz as bandwidth. Dimensions of the Y-Junction power splitter are $6.8^{star }6^{star }0.508mathrm {m}mathrm {m}^{3}$. Due to its reflection coefficient, dimensions, transmission coefficient and bandwidth this power splitter is suitable for V-band millimeter wave applications like Wireless LAN and RADAR applications for what today’s need of society.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132200153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Nonlinear Electron Transport Mobility in GaAs/Al x Ga1-x As Square - Parabolic Double Quantum Well MODFET Structure GaAs/Al x Ga1-x As平方-抛物双量子阱MODFET结构中的非线性电子输运迁移率
2018 4th International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2018-03-01 DOI: 10.1109/ICDCSYST.2018.8605171
N. Sahoo, T. Sahu, A. K. Panda
{"title":"Nonlinear Electron Transport Mobility in GaAs/Al x Ga1-x As Square - Parabolic Double Quantum Well MODFET Structure","authors":"N. Sahoo, T. Sahu, A. K. Panda","doi":"10.1109/ICDCSYST.2018.8605171","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605171","url":null,"abstract":"We study doping dependence nonlinear electron transport mobility $mu _{t}$ in a GaAslAlxGal-x4s double quantum well MODFET structure. We consider square (parabolic) well towards the substrate (surface) side of the structure. The side barrier towards the substrate (surface) is modulation delta doped with Si of doping concentration $Nd_{sub}(Nd_{sur})$. We analyze $mu _{t}$ as function of $Nd_{sub}$ (keeping $Nd_{sur}$ constant) by considering different scattering mechanisms such as: ionized impurity (Imp-), alloy disorder (Al-) and interface roughness $(Ir-)$. We show that $mu _{t}$ is mainly decided by $mu i^{mp}$ whereas $mu i^{r}$ reduces the overall $mu _{t}$. We also show that nonlinear $mu _{t}$ can be achieved during double subband occupancy and attain minimum at the anticrossing of subband states which occur for $Nd_{sub} lt Nd_{sur}$. There is also a sudden enhancement $ofmu _{t}$ due to the cease of intersubband effects at $(Nd_{sub})_{trans}$ where double to single subband occupancy takes place. It is gratifying to show that increasing well width $w$ enhances $mu _{t}$ as well as transition from double to single occur for higher value of $(Nd_{sub})_{trms}$. Our results can be utilized for the analysis of improvement of channel conductivity of double quantum well MODFET structure.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130511034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
GAA-CNTFET based Single/Dual-Channel and Single/Dual-Chirality digital gates for High Speed and Low Power Application 基于GAA-CNTFET的单/双通道和单/双手性数字门,用于高速低功耗应用
2018 4th International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2018-03-01 DOI: 10.1109/ICDCSYST.2018.8605137
Singh Rohitkumar Shailendra, V. N. Ramakrishnan
{"title":"GAA-CNTFET based Single/Dual-Channel and Single/Dual-Chirality digital gates for High Speed and Low Power Application","authors":"Singh Rohitkumar Shailendra, V. N. Ramakrishnan","doi":"10.1109/ICDCSYST.2018.8605137","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605137","url":null,"abstract":"Gate All-Around Carbon Nanotube Field Effect Transistor (GAA-CNTFET) is one of the promising transistors to substitute traditional MOSFET. This paper presents universal logic gates based on GAA-CNTFET with different chiral indexes and different number of channel selection for high speed and low power digital application. The simulation tool is used for design and simulation of GAA-CNTFET based basic logic gates. The power consumption and total delay for basic logic gates is calculated for different chirality indexes and different channel selection. From our results, we report that when we increase the chiral vector of CNT; delay increases in digital logic gates. Single chirality (25, 25, 0) based digital logic gates provide minimum delay, similarly dual chirality (25, 22, 0) type digital logic gates exhibits minimum delay. Whereas (14, 14, 0) and (16, 14, 0) chirality delivers low power consumption.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127616219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis of Dynamic Models of a STT-MRAM STT-MRAM的动力学模型分析
2018 4th International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2018-03-01 DOI: 10.1109/ICDCSYST.2018.8605161
Bettymol Mathew, N. M. Siva Mangai
{"title":"Analysis of Dynamic Models of a STT-MRAM","authors":"Bettymol Mathew, N. M. Siva Mangai","doi":"10.1109/ICDCSYST.2018.8605161","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605161","url":null,"abstract":"STT-MRAM has the potential to become a universal memory owing to many advantages it has as compared to the existing memory technologies. Several models, both static as well as dynamic models have been developed amongst which dynamic models have been known to display more accurate behaviour. In this paper, we have chosen two such dynamic models already developed and available and observed and verified their transient response.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115599518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A FAM-2D RLS based smart Massive MIMO system 基于FAM-2D RLS的智能大规模MIMO系统
2018 4th International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2018-03-01 DOI: 10.1109/ICDCSYST.2018.8605128
Arun Joy, Athira jess, Irin Sajan, Priscilla Grace
{"title":"A FAM-2D RLS based smart Massive MIMO system","authors":"Arun Joy, Athira jess, Irin Sajan, Priscilla Grace","doi":"10.1109/ICDCSYST.2018.8605128","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605128","url":null,"abstract":"In this paper we implement a Fast Array Multichannel 2D Recursive Least Square (FAM 2D-RLS) based smart antenna system for massive MIMO. A rectangular antenna array in the X-Y plane is considered. The direction of arrival (DOA) is estimated using MUSIC algorithm. The estimated DOA is used by the adaptive beamformer to generate beams that have maximum gain in the direction of receiver and nulls in the direction of interferes. The computational complexity is calculated and convergence performance is simulated and compared with standard adaptive algorithms. It is seen that convergence performance of FAM 2D-RLS is similar to that of a standard RLS algorithm while the computational complexity is comparable to that of standard Least Mean Square algorithm (LMS). It is also observed that the computational cost of the adaptive filter is directly proportional to the total number of antennas in the antenna array. Hence the contributions in this paper is highly relevant in the case of massive MIMO systems. The simulations are performed in MATLAU & SystemVue.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122110377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
RF Performance comparison of Dual Material Gate (DMG) and Conventional AlGaN/GaN High Electron Mobility Transistor 双材料栅极(DMG)与传统AlGaN/GaN高电子迁移率晶体管的射频性能比较
2018 4th International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2018-03-01 DOI: 10.1109/ICDCSYST.2018.8605122
Nisha Chugh, Manoj Kumar, M. Bhattacharya, R. Gupta
{"title":"RF Performance comparison of Dual Material Gate (DMG) and Conventional AlGaN/GaN High Electron Mobility Transistor","authors":"Nisha Chugh, Manoj Kumar, M. Bhattacharya, R. Gupta","doi":"10.1109/ICDCSYST.2018.8605122","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605122","url":null,"abstract":"This paper presents a simulation based analysis of the RF performance of dual material gate (DMG) AlGaN/GaN HEMT and its performance is compared with that of Single Material Gate (SMG) AlGaN/GaN HEMT by using two-dimensional ATLAS TCAD device simulation. The simulation results demonstrate that the DMG HEMT exhibits much higher drain current, higher transconductance, higher cut-off frequency as compared to the conventional HEMT due to improved velocity of carriers in the channel and reduced SCEs. Also, an improvement in carrier transport efficiency is achieved by the uniform electric field along the channel. This Tuning of DMG HEMT in terms of the different gate-source voltage and drain voltage has been carried out to enhance the drive current, transconductance and the cut-off frequency illustrating the superior performance of DMG HEMT as compared to SMG HEMT for future high speed, microwave, digital and analog applications.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125075791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design and Study of Memristor based Non-autonomous Chua's circuit 基于非自治蔡氏电路的忆阻器设计与研究
2018 4th International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2018-03-01 DOI: 10.1109/ICDCSYST.2018.8605075
T. S. Ghouse Basha, I. R. Mohamed, A. Chithra
{"title":"Design and Study of Memristor based Non-autonomous Chua's circuit","authors":"T. S. Ghouse Basha, I. R. Mohamed, A. Chithra","doi":"10.1109/ICDCSYST.2018.8605075","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605075","url":null,"abstract":"In this work, a new memristor based non-autonomous chaotic oscillator is designed from the Chua's circuit, by replacing Chua's diode with a first order memristive diode bridge. The dynamical behaviors of the circuit are investigated via real-time hardware circuit. Further, the circuit is driven by sinusoidal and non-sinusoidal forces in order to explore the variety of nonlinear dynamics. The system exhibits complex dynamical behaviors including period doubling, multiple attractors. They are investigated in terms of phase space trajectory plots, frequency spectra and as well as time series plot.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125685667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of Chopper Stabilized Preamplifier for ECG monitoring System 心电监测系统斩波稳定前置放大器的设计
2018 4th International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2018-03-01 DOI: 10.1109/ICDCSYST.2018.8605168
A. Uma, C. Selvagangai, P. Kalpana
{"title":"Design of Chopper Stabilized Preamplifier for ECG monitoring System","authors":"A. Uma, C. Selvagangai, P. Kalpana","doi":"10.1109/ICDCSYST.2018.8605168","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605168","url":null,"abstract":"This paper proposes a high gain Chopper stabilized preamplifier for the ECG monitoring system. In analog based ECG acquisition front end, a low noise amplifier is required to have a large dynamic range of 0.1 to 250Hz. A Chopper stabilized preamplifier is proposed which has high gain and removes the flicker noise. In chopper stabilized preamplifier, the input signal is modulated, amplified and in the back end it is demodulated to produce the noiseless signal. The performance of proposed preamplifier is compared with the conventional structure and it shows that the modified Preamplifier has high gain. The operating frequency of the preamplifier is 250H: The proposed preamplifier has better Total Harmonic Distortion than conventional structures. The simulations are done in the Cadence tool with 180nm technology in virtuoso platform.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133641730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Low-Power High Linear RF Mixer for 2.4GHz Low-Rate WPAN Applications 一种用于2.4GHz低速率WPAN应用的低功耗高线性射频混频器
2018 4th International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2018-03-01 DOI: 10.1109/ICDCSYST.2018.8605165
S. Gladson, K. Alekhya, M. Bhaskar
{"title":"A Low-Power High Linear RF Mixer for 2.4GHz Low-Rate WPAN Applications","authors":"S. Gladson, K. Alekhya, M. Bhaskar","doi":"10.1109/ICDCSYST.2018.8605165","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605165","url":null,"abstract":"The IEEE 802.15.4 Low-Rate Wireless Personal Area Network (LR-WPAN) standard dictates stringent requirements on performance and cost. The standard is designed to cover a small area of coverage (10m), within the personal accessible space of the user. The LR-WPAN systems must be smaller in size to fit in the accessible area and also must be able to communicate with other wireless systems nearby, thus creating a wireless personal area network for the user. This personal communication network is the base for the Internet-of-Things (IoT) applications. These wireless systems must be of low cost and also provide the highest quality of performance to the user. A low cost chip poses the challenge of reduction in the area of the Silicon chip without affecting the performance of the system. This challenge is addressed in this paper by introducing a low cost, low-power, high-performance mixer for the LR-WPAN application. The proposed mixer circuit employs bulk biasing and active degeneration for linearity improvement. The analysis of the circuit for the gain and linearity is given for the understanding of the circuit operation. The mixer is designed and implemented in 180nm UMC CMOS technology using Cadence SpectreRF tool with probe pads for bare die measurement. The mixer offers a conversion gain of 15. 08dB with the output referred third-order intercept point (OIP3) at 21. 28dBm and a single-sideband (SSB) noise figure (NF) of 14.01dB. The performance is achieved by consuming only 3. 52mW of power from a 1. 8V supply. The Figure-of-Merit is calculated for performance comparison, and it is found to be better than some of the other mixer circuits reported in the literature. The proposed mixer circuit occupies a core area of 23.98 μm × 49.95 μm without the power rails and the probe pads.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129026560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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