{"title":"A Low-Power High Linear RF Mixer for 2.4GHz Low-Rate WPAN Applications","authors":"S. Gladson, K. Alekhya, M. Bhaskar","doi":"10.1109/ICDCSYST.2018.8605165","DOIUrl":null,"url":null,"abstract":"The IEEE 802.15.4 Low-Rate Wireless Personal Area Network (LR-WPAN) standard dictates stringent requirements on performance and cost. The standard is designed to cover a small area of coverage (10m), within the personal accessible space of the user. The LR-WPAN systems must be smaller in size to fit in the accessible area and also must be able to communicate with other wireless systems nearby, thus creating a wireless personal area network for the user. This personal communication network is the base for the Internet-of-Things (IoT) applications. These wireless systems must be of low cost and also provide the highest quality of performance to the user. A low cost chip poses the challenge of reduction in the area of the Silicon chip without affecting the performance of the system. This challenge is addressed in this paper by introducing a low cost, low-power, high-performance mixer for the LR-WPAN application. The proposed mixer circuit employs bulk biasing and active degeneration for linearity improvement. The analysis of the circuit for the gain and linearity is given for the understanding of the circuit operation. The mixer is designed and implemented in 180nm UMC CMOS technology using Cadence SpectreRF tool with probe pads for bare die measurement. The mixer offers a conversion gain of 15. 08dB with the output referred third-order intercept point (OIP3) at 21. 28dBm and a single-sideband (SSB) noise figure (NF) of 14.01dB. The performance is achieved by consuming only 3. 52mW of power from a 1. 8V supply. The Figure-of-Merit is calculated for performance comparison, and it is found to be better than some of the other mixer circuits reported in the literature. The proposed mixer circuit occupies a core area of 23.98 μm × 49.95 μm without the power rails and the probe pads.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICDCSYST.2018.8605165","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
The IEEE 802.15.4 Low-Rate Wireless Personal Area Network (LR-WPAN) standard dictates stringent requirements on performance and cost. The standard is designed to cover a small area of coverage (10m), within the personal accessible space of the user. The LR-WPAN systems must be smaller in size to fit in the accessible area and also must be able to communicate with other wireless systems nearby, thus creating a wireless personal area network for the user. This personal communication network is the base for the Internet-of-Things (IoT) applications. These wireless systems must be of low cost and also provide the highest quality of performance to the user. A low cost chip poses the challenge of reduction in the area of the Silicon chip without affecting the performance of the system. This challenge is addressed in this paper by introducing a low cost, low-power, high-performance mixer for the LR-WPAN application. The proposed mixer circuit employs bulk biasing and active degeneration for linearity improvement. The analysis of the circuit for the gain and linearity is given for the understanding of the circuit operation. The mixer is designed and implemented in 180nm UMC CMOS technology using Cadence SpectreRF tool with probe pads for bare die measurement. The mixer offers a conversion gain of 15. 08dB with the output referred third-order intercept point (OIP3) at 21. 28dBm and a single-sideband (SSB) noise figure (NF) of 14.01dB. The performance is achieved by consuming only 3. 52mW of power from a 1. 8V supply. The Figure-of-Merit is calculated for performance comparison, and it is found to be better than some of the other mixer circuits reported in the literature. The proposed mixer circuit occupies a core area of 23.98 μm × 49.95 μm without the power rails and the probe pads.