GAA-CNTFET based Single/Dual-Channel and Single/Dual-Chirality digital gates for High Speed and Low Power Application

Singh Rohitkumar Shailendra, V. N. Ramakrishnan
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Abstract

Gate All-Around Carbon Nanotube Field Effect Transistor (GAA-CNTFET) is one of the promising transistors to substitute traditional MOSFET. This paper presents universal logic gates based on GAA-CNTFET with different chiral indexes and different number of channel selection for high speed and low power digital application. The simulation tool is used for design and simulation of GAA-CNTFET based basic logic gates. The power consumption and total delay for basic logic gates is calculated for different chirality indexes and different channel selection. From our results, we report that when we increase the chiral vector of CNT; delay increases in digital logic gates. Single chirality (25, 25, 0) based digital logic gates provide minimum delay, similarly dual chirality (25, 22, 0) type digital logic gates exhibits minimum delay. Whereas (14, 14, 0) and (16, 14, 0) chirality delivers low power consumption.
基于GAA-CNTFET的单/双通道和单/双手性数字门,用于高速低功耗应用
栅极全能碳纳米管场效应晶体管(GAA-CNTFET)是极有希望取代传统MOSFET的晶体管之一。本文提出了基于GAA-CNTFET的具有不同手性指数和不同通道数选择的通用逻辑门,用于高速低功耗数字应用。该仿真工具用于GAA-CNTFET基本逻辑门的设计与仿真。计算了不同手性指数和不同通道选择下基本逻辑门的功耗和总延时。从我们的结果来看,我们报告当我们增加碳纳米管的手性矢量时;数字逻辑门的延迟增加。基于单手性(25,25,0)的数字逻辑门提供最小的延迟,类似地,双手性(25,22,0)型数字逻辑门具有最小的延迟。而(14,14,0)和(16,14,0)手性提供低功耗。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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