2012 2nd IEEE CPMT Symposium Japan最新文献_第9页

Study of the insertion loss of a differential pair of through holes for the 25-Gbps serial interconnect 25gbps串行互连差分通孔对插入损耗的研究

2012 2nd IEEE CPMT Symposium Japan Pub Date : 2012-12-01 DOI: 10.1109/ICSJ.2012.6523463

G. Shinkai, S. Muraoka, M. Yagu, Y. Uematsu, H. Osaka

{"title":"Study of the insertion loss of a differential pair of through holes for the 25-Gbps serial interconnect","authors":"G. Shinkai, S. Muraoka, M. Yagu, Y. Uematsu, H. Osaka","doi":"10.1109/ICSJ.2012.6523463","DOIUrl":"https://doi.org/10.1109/ICSJ.2012.6523463","url":null,"abstract":"To design future high-speed interconnects that operate above 25 Gbps, accurate scattering parameters (s-parameters) of structures, such as through holes, are necessary. We estimated the s-parameters of a differential pair of through holes by using the de-embedding technique to eliminate undesirable loss and delay in the feed lines connected to the through holes. By comparing this insertion loss and the estimated insertion loss of a corresponding electromagnetic (EM) simulation model, we found that the distance between the center of the drill holes and the center of their clearance could be a reason for the increase in the insertion loss of the through holes in addition to the open stub effect above 20 GHz. We also discuss the reason for the error in the de-embedding from the viewpoint of measurement repeatability. We estimated contact resistance, parasitic capacitance, and parasitic inductance at the air coplanar (ACP) probe tips from the measured s-parameters. The result shows that these parameters varied about 0.1 Ω, 0.1 nH, and 0.05 pF due to reasons such as the contact condition or the flatness of the PCB. To mitigate these parasitic lumped elements, probes with smaller tips are preferable when we measure the s-parameters of structures for de-embedding.","PeriodicalId":174050,"journal":{"name":"2012 2nd IEEE CPMT Symposium Japan","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128873243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Wide bus chip-to-chip interconnection technology using fine pitch bump joint array for 3D LSI chip stacking 采用小间距凸接阵列的宽总线芯片对芯片互连技术用于3D LSI芯片堆叠

2012 2nd IEEE CPMT Symposium Japan Pub Date : 2012-12-01 DOI: 10.1109/ICSJ.2012.6523418

M. Aoyagi, F. Imura, S. Nemoto, N. Watanabe, F. Kato, K. Kikuchi, H. Nakagawa, M. Hagimoto, H. Uchida, Y. Matsumoto

引用次数: 8

Build-up electrical insulation material for high speed & high-frequency 用于高速和高频的电气绝缘材料

2012 2nd IEEE CPMT Symposium Japan Pub Date : 2012-12-01 DOI: 10.1109/ICSJ.2012.6523466

T. Kunikawa, T. Tanaka, H. Kouyanagi, K. Shirahase

{"title":"Build-up electrical insulation material for high speed & high-frequency","authors":"T. Kunikawa, T. Tanaka, H. Kouyanagi, K. Shirahase","doi":"10.1109/ICSJ.2012.6523466","DOIUrl":"https://doi.org/10.1109/ICSJ.2012.6523466","url":null,"abstract":"The demand for high performance build-up electrical insulation materials, used in IC package substrates, is increasing due to ever-increasing speed signal processing and density of LSIs due to requirement for faster information and communication equipment in recent years. These LSIs with signal travelling at high speeds also causes GHz band signal to travel through the package substrate. If the dielectric loss tangent of the insulation material is large, not only will it lead to high signal losses, it will also cause other problems such as increase in heat releases. Furthermore, GHz band signal travelling at high speed causes large transmission losses at the surface of the conductor due to skin effect and this is especially true when the surface smoothness of the conductor is rough triggering a signal delay. To countermeasure these problems, build up insulation material that has both low dielectric loss tangent and enables smoother conductor surfaces after processing, was developed achieving very low signal loss of -1.38dB/inch at 10GHz using microstrip line. Here we report the result of the low transmission loss of the newly developed material by microstrip line and the successful result of isolating the effect of low dielectric loss tangent and conductor smoothness that affect transmission loss. Finally we report a novel insulation material that achieves further low transmission loss by having dielectric loss tangent of 0.004 level with conductor surface roughness of less than 100 nm.","PeriodicalId":174050,"journal":{"name":"2012 2nd IEEE CPMT Symposium Japan","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127812261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Influence of a foam supporter on passive intermodulation measurement using standing-wave coaxial tube method 泡沫支架对驻波同轴管法无源互调测量的影响

2012 2nd IEEE CPMT Symposium Japan Pub Date : 2012-12-01 DOI: 10.1109/ICSJ.2012.6523469

D. Ishibashi, N. Kuga

引用次数: 0

Using nano-porous Au-Ag sheets as a joint layer for low-temperature Au-Au bonding 采用纳米多孔Au-Ag片作为低温Au-Au键合的连接层

2012 2nd IEEE CPMT Symposium Japan Pub Date : 2012-12-01 DOI: 10.1109/ICSJ.2012.6523449

H. Mimatsu, J. Mizuno, T. Kasahara, M. Saito, H. Nishikawa, S. Shoji

引用次数: 2

Prognostic health monitoring method for printed circuit boards subjected to random cyclic loads 随机循环载荷作用下印刷电路板的预测健康监测方法

2012 2nd IEEE CPMT Symposium Japan Pub Date : 2012-12-01 DOI: 10.1109/ICSJ.2012.6523421

K. Hirohata, Y. Hisakuni, T. Omori, M. Mukai

引用次数: 0

Cu wire bonding knows no limit - 28 nm is qualified 铜线键合没有限制，28nm是合格的

2012 2nd IEEE CPMT Symposium Japan Pub Date : 2012-12-01 DOI: 10.1109/ICSJ.2012.6523390

B. Appelt, A. Tseng, S. Uegaki, L. Huang

引用次数: 1

Phase change cooling for energy-efficient ICT systems 节能ICT系统的相变冷却

2012 2nd IEEE CPMT Symposium Japan Pub Date : 2012-12-01 DOI: 10.1109/ICSJ.2012.6523472

M. Yoshikawa, K. Inaba, A. Matsunaga, H. Sakamoto

引用次数: 1

Three-dimensional integration scheme using hybrid wafer bonding and via-last TSV process 采用混合晶圆键合和过孔TSV工艺的三维集成方案

2012 2nd IEEE CPMT Symposium Japan Pub Date : 2012-12-01 DOI: 10.1109/ICSJ.2012.6523456

K. Takeda, M. Aoki, K. Hozawa, F. Furuta, A. Yanagisawa, H. Kikuchi, T. Mitsuhashi, H. Kobayashi

引用次数: 1

Electrochemical analysis of cathode in TSV copper electroplating TSV镀铜阴极的电化学分析

2012 2nd IEEE CPMT Symposium Japan Pub Date : 2012-12-01 DOI: 10.1109/ICSJ.2012.6523399

H. Cao, Xue Feng, Qi Sun, Wei-Xiong Luo, Huiqin Ling, J. Sun, Ming Li

引用次数: 3