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Novel EMI shielding methodology on highly integration SiP module 高集成度SiP模块的新型电磁干扰屏蔽方法
2012 2nd IEEE CPMT Symposium Japan Pub Date : 2012-12-01 DOI: 10.1109/ICSJ.2012.6523433
Kuo-Hsien Liao, A. Chan, S. C. Hsien, Lin I-Chia, Huang Hsin Wen
{"title":"Novel EMI shielding methodology on highly integration SiP module","authors":"Kuo-Hsien Liao, A. Chan, S. C. Hsien, Lin I-Chia, Huang Hsin Wen","doi":"10.1109/ICSJ.2012.6523433","DOIUrl":"https://doi.org/10.1109/ICSJ.2012.6523433","url":null,"abstract":"SiP (System-in-Package) modules play an important role to make electronic portable devices thinner, integrate more functions and reduce time to market. However, the high density of electrical functions usually causes electromagnetic noise interference (EMI) on nearby components and high level of total radiated EMI from the system product. Traditional SiP modules use a metal can to reduce EMI and this often results in an increase in both module footprint and thickness. Conformal shielding is a novel methodology to reduce EMI on molded SiP modules by using a sputtered thin metal layer on the module's top and side. In previous work, we evaluated the shielding effectiveness for single compartment module for both near field and far field conditions. As modules may contain multiple functionalities which may need to be shielded from one another, we have developed a process to construct shielded compartments by the conductive barrier inside the package, providing a way to reduce the product design area requirement. We have prepared a test vehicle with two compartments separated and with antenna coupons inside each compartment. In the paper, we present the process characterization result and measurements of the shielding effectiveness of the entire module as well as between the compartments and thereby demonstrate the advantages of SiP modules with compartment shielding.","PeriodicalId":174050,"journal":{"name":"2012 2nd IEEE CPMT Symposium Japan","volume":"260 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116240819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Heterogeneous integration of MEMS sensor array and CMOS readout IC with Through Silicon Via interconnects 通过硅孔互连的MEMS传感器阵列和CMOS读出集成电路的异构集成
2012 2nd IEEE CPMT Symposium Japan Pub Date : 2012-12-01 DOI: 10.1109/ICSJ.2012.6523398
Qian Wang, S. Xie, Tao Wang, Jian Cai, Ziyu Liu, Dong Wu, Mengyun Yue, Zheyao Wang, Shuidi Wang, Songliang Jia
{"title":"Heterogeneous integration of MEMS sensor array and CMOS readout IC with Through Silicon Via interconnects","authors":"Qian Wang, S. Xie, Tao Wang, Jian Cai, Ziyu Liu, Dong Wu, Mengyun Yue, Zheyao Wang, Shuidi Wang, Songliang Jia","doi":"10.1109/ICSJ.2012.6523398","DOIUrl":"https://doi.org/10.1109/ICSJ.2012.6523398","url":null,"abstract":"Through Silicon Via (TSV) forms electrical feedthrough and makes it possible to vertically stack chips with various functions which including logic, memory, analog and MEMS etc. This paper presents a TSV 3D- heterogeneous integration structure of MEMS sensor array with CMOS readout IC (ROIC) and its fabrication technology. Surface micromaching of sensor array are co-designed with TSV fabrication processes to enable TSVs for electrical signals output from backside in sensor chip, sensor chip and its corresponding ROIC chip are vertically stacked, and chip to chip interconnection is achieved by Cu/Sn-Cu microbump bonding. The stacked structure are then assembled to relized MEMS-CMOS 3D heterogeneous integration. Overall, the present work describes an approach for high density MEMS integration.","PeriodicalId":174050,"journal":{"name":"2012 2nd IEEE CPMT Symposium Japan","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122556911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Proposal and analysis of three-phase filter by using mixed-mode S-parameter based on Fortescue transformation 基于Fortescue变换的混合模式s参数三相滤波器的提出与分析
2012 2nd IEEE CPMT Symposium Japan Pub Date : 2012-12-01 DOI: 10.1109/ICSJ.2012.6523434
Y. Fujishiro, K. Koshiji
{"title":"Proposal and analysis of three-phase filter by using mixed-mode S-parameter based on Fortescue transformation","authors":"Y. Fujishiro, K. Koshiji","doi":"10.1109/ICSJ.2012.6523434","DOIUrl":"https://doi.org/10.1109/ICSJ.2012.6523434","url":null,"abstract":"In this paper, we propose a new method for evaluation of a three-phase filter, utilizing a “mixed-mode S-parameter based on Fortescue transformation.” Because the positive phase sequence is the main component of current in a three-phase circuit, it is necessary to be able to analyze this response. Moreover, it is important to assess the effects of the zero phase sequence in order to investigate both conductive and radiative noise. To perform these analyses, it is useful to transform voltage and current into symmetrical coordinates, which leads to the mixed-mode S-parameter. Measurement examples based on this method are given in this paper. Because three-phase filters with cyclic symmetry have zero matrices as off-diagonal blocks in the mixed-mode S-matrix, each phase sequence becomes independent and non-interactive. Accordingly, by using the multi-section theorem, we can decompose the filter into modal equivalent circuits; the results calculated with these circuits agree well with those obtained from the measurement.","PeriodicalId":174050,"journal":{"name":"2012 2nd IEEE CPMT Symposium Japan","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130411961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
3D system simulation study of power integrity using Si interposer with distribution TSV decoupling capacitors 分布式TSV去耦电容硅介面电源完整性的三维系统仿真研究
2012 2nd IEEE CPMT Symposium Japan Pub Date : 2012-12-01 DOI: 10.1109/ICSJ.2012.6523458
K. Kohno, Y. Kitamura, T. Kamada, J. Ohara, Y. Akiyama, C. Ueda, K. Otsuka
{"title":"3D system simulation study of power integrity using Si interposer with distribution TSV decoupling capacitors","authors":"K. Kohno, Y. Kitamura, T. Kamada, J. Ohara, Y. Akiyama, C. Ueda, K. Otsuka","doi":"10.1109/ICSJ.2012.6523458","DOIUrl":"https://doi.org/10.1109/ICSJ.2012.6523458","url":null,"abstract":"Improvements of power integrity (PI) on high-speed system have been studied from the point view of many structures in huge papers[1][2][3]. In this study, the PI simulation for the A-D mixed 3D stack chip system by TSV is done in many kinds of power sources. We already studied on the interposer with large area MIM capacitor was effective for the 3D system [4][5], that understood as an area structure made lower input impedance ever GHz region. As a result, we can find which the input impedance is related largely with the DeCap TSV distribution pitch. Consideration of approach wiring to distributed DeCap TSVs is the key issue for the better PI performance as the result.","PeriodicalId":174050,"journal":{"name":"2012 2nd IEEE CPMT Symposium Japan","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121682816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low temperature bonding using sub-micron Au particles for wafer-level MEMS packaging 采用亚微米金颗粒低温键合用于晶圆级MEMS封装
2012 2nd IEEE CPMT Symposium Japan Pub Date : 2012-12-01 DOI: 10.1109/ICSJ.2012.6523451
S. Ito, J. Mizuno, H. Ishida, T. Ogashiwa, Y. Kanehira, H. Murai, F. Wakai, S. Shoji
{"title":"Low temperature bonding using sub-micron Au particles for wafer-level MEMS packaging","authors":"S. Ito, J. Mizuno, H. Ishida, T. Ogashiwa, Y. Kanehira, H. Murai, F. Wakai, S. Shoji","doi":"10.1109/ICSJ.2012.6523451","DOIUrl":"https://doi.org/10.1109/ICSJ.2012.6523451","url":null,"abstract":"In this study, low temperature bonding using sub-micron Au particles was investigated. Two types of Au particles with different average mean diameter of 0.1 μm and 0.3 μm were used. The 0.1 μm Au particles were sintered at lower temperature than that of 0.3 μm. These particles have an advantage of low sintering temperature under 200 °C, and compensating surface roughness. The compression deformation properties of Au particles were measured. They were compressed to around 3 and 5 μm at 30 and 100 MPa applied pressure, respectively. Chip-level bonding was performed with sealing rings of Au particles. The tensile strength of 55.2 MPa was obtained by bonding under applied pressure of 50 MPa at 100 °C. As the evaluation of hermeticity, gross leak test was performed for bonded chips with single, double, and triple sealing rings.","PeriodicalId":174050,"journal":{"name":"2012 2nd IEEE CPMT Symposium Japan","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126406742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Transient response characteristics of through silicon via in high resistivity silicon interposer 高阻硅中间体中通孔硅的瞬态响应特性
2012 2nd IEEE CPMT Symposium Japan Pub Date : 2012-12-01 DOI: 10.1109/ICSJ.2012.6523459
N. Watanabe, C. Ueda, F. Fujii, Y. Akiyama, K. Kikuchi, Y. Kitamura, T. Gomyo, T. Ookubo, T. Koyama, T. Kamada, M. Aoyagi, K. Otsuka
{"title":"Transient response characteristics of through silicon via in high resistivity silicon interposer","authors":"N. Watanabe, C. Ueda, F. Fujii, Y. Akiyama, K. Kikuchi, Y. Kitamura, T. Gomyo, T. Ookubo, T. Koyama, T. Kamada, M. Aoyagi, K. Otsuka","doi":"10.1109/ICSJ.2012.6523459","DOIUrl":"https://doi.org/10.1109/ICSJ.2012.6523459","url":null,"abstract":"We investigated the transient response characteristic of through silicon via (TSV) in a high-resistivity silicon interposer. For this investigation, signal ground (SG)-TSV-chain pairs in high-resisitivity silicon (>1000 Ω·cm) were prepared. Various pulse waves (swing: -1.8-0 V or 0-+1.8 V, pulse width: 250 ps-100 ms, duty ratio: 1/1) were applied to a SG-TSV-chain pair by using a pulse generator, and output signal was obtained using a sampling oscilloscope. From the rise and fall time of output signal, it was found that the change in transient response characteristic according to the frequency and voltage of the applied pulse wave was very small. This result demonstrates that the change in TSV capacitance with the input signal is very small and that high-resistivity silicon is effective for high speed signal processing.","PeriodicalId":174050,"journal":{"name":"2012 2nd IEEE CPMT Symposium Japan","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132317070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of energy relaxation time on heat generation in silicon with electro-thermal analysis 用电热分析研究能量松弛时间对硅中热生成的影响
2012 2nd IEEE CPMT Symposium Japan Pub Date : 2012-12-01 DOI: 10.1109/ICSJ.2012.6523473
T. Hatakeyama, R. Kibushi, M. Ishizuka
{"title":"Impact of energy relaxation time on heat generation in silicon with electro-thermal analysis","authors":"T. Hatakeyama, R. Kibushi, M. Ishizuka","doi":"10.1109/ICSJ.2012.6523473","DOIUrl":"https://doi.org/10.1109/ICSJ.2012.6523473","url":null,"abstract":"This paper describes heat generation in semiconductor depending on energy relaxation time between electron and lattice. Recently, power semiconductor devices are widely used in several areas, for example car electronics. Heat generation density in electrical devices has been increased with downsizing electrical devices. Then, thermal management of semiconductor devices is becoming key issue for further development of electrical devices. In this paper, estimation of heat generation in silicon under high electric filed was focused. Under high electric field, electron energy (electron temperature) becomes much higher than lattice energy (lattice temperature). Therefore, electro-thermal analysis was employed to consider non-equilibrium state between electron temperature and lattice temperature. Energy relaxation time between electron and lattice was varied as parameter and impact of energy relaxation time on estimated heat generation density was discussed.","PeriodicalId":174050,"journal":{"name":"2012 2nd IEEE CPMT Symposium Japan","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132470086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High-stability 25 Gb/s optical transceiver module with flexible polymer wave guide for optical interconnection 高稳定性的25gb /s光收发模块，采用柔性聚合物波导，实现光互连
2012 2nd IEEE CPMT Symposium Japan Pub Date : 2012-12-01 DOI: 10.1109/ICSJ.2012.6523380
N. Matsushima, T. Takai, D. Kawamura, Y. Matsuoka, Yong Lee, N. Chujo, T. Takemoto, H. Yamashita, T. Sugawara, T. Yazaki, S. Tsuji
{"title":"High-stability 25 Gb/s optical transceiver module with flexible polymer wave guide for optical interconnection","authors":"N. Matsushima, T. Takai, D. Kawamura, Y. Matsuoka, Yong Lee, N. Chujo, T. Takemoto, H. Yamashita, T. Sugawara, T. Yazaki, S. Tsuji","doi":"10.1109/ICSJ.2012.6523380","DOIUrl":"https://doi.org/10.1109/ICSJ.2012.6523380","url":null,"abstract":"A high-stability and high-speed optical transceiver module for a chip-to-chip optical interconnection has been developed. The stability of optical power output is provided by optimizing the packaging structure snd thus reducing deformation of the module resulting from the bimetallic effect. (Degradation of optical coupling efficiency is reduced to 0.15 dB by limiting variations in temperature to a level between 25 and 75 deg C). High-speed(25 Gb/s) transmission is obtained by high transmitting rate devices and low-loss electrical wiring.","PeriodicalId":174050,"journal":{"name":"2012 2nd IEEE CPMT Symposium Japan","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129965690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Measurement results of substrate bias dependency on Negative Bias Temperature Instability degradation in a 65 nm process 衬底偏压对负偏压温度不稳定性退化的影响
2012 2nd IEEE CPMT Symposium Japan Pub Date : 2012-12-01 DOI: 10.1109/ICSJ.2012.6523441
S. Tanihiro, M. Yabuuchi, K. Kobayashi
{"title":"Measurement results of substrate bias dependency on Negative Bias Temperature Instability degradation in a 65 nm process","authors":"S. Tanihiro, M. Yabuuchi, K. Kobayashi","doi":"10.1109/ICSJ.2012.6523441","DOIUrl":"https://doi.org/10.1109/ICSJ.2012.6523441","url":null,"abstract":"The transistor size keeps shrinking by Moore's law and timing degradation of the scaled transistors is becoming critical. Recently, the scaling of CMOS technology increases the effect of NBTI (Negative Bias Temperature Instability) in PMOS. NBTI is an important reliability issue for analog as well as digital CMOS circuits. As transistors are scaled refined, the impact of NBTI becomes more critical. This paper deals with relationship between NBTI and the substrate bias. If the substrate bias go a forward, degradation of NBTI is accelerated. We show measurement results of degradation due to NBTI according to the forward and reverse body biases.","PeriodicalId":174050,"journal":{"name":"2012 2nd IEEE CPMT Symposium Japan","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133253725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Solid-state bonding using metallic cone layer for interconnection 使用金属锥层进行互连的固态键合
2012 2nd IEEE CPMT Symposium Japan Pub Date : 2012-12-01 DOI: 10.1109/ICSJ.2012.6523396
Ming Li, A. Hu, Zhuo Chen, Qin Lu, Wenjing Zhang, T. Suga, Yinghui Wang, E. Higurashi, M. Fujino
{"title":"Solid-state bonding using metallic cone layer for interconnection","authors":"Ming Li, A. Hu, Zhuo Chen, Qin Lu, Wenjing Zhang, T. Suga, Yinghui Wang, E. Higurashi, M. Fujino","doi":"10.1109/ICSJ.2012.6523396","DOIUrl":"https://doi.org/10.1109/ICSJ.2012.6523396","url":null,"abstract":"This paper describes the feasibility of using metallic cone layer in solid-state bonding with Sn-based solder. At temperature below the melting point of Sn, both Ni cones and Cu cones were found successful in forming robust joints with good bonding strength and compact interfaces. This method is also compatible with high-density micro bump interconnecting. Studies have also been carried out in combination with surface activation bonding. Mechanical insertion and controllable interfacial reactions functioning as key factors for realization of the bonding method were emphasized through theoretical study. This bonding method is expected to be potential for the applications in 3D integration.","PeriodicalId":174050,"journal":{"name":"2012 2nd IEEE CPMT Symposium Japan","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127383761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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