3D system simulation study of power integrity using Si interposer with distribution TSV decoupling capacitors

Abstract

Improvements of power integrity (PI) on high-speed system have been studied from the point view of many structures in huge papers[1][2][3]. In this study, the PI simulation for the A-D mixed 3D stack chip system by TSV is done in many kinds of power sources. We already studied on the interposer with large area MIM capacitor was effective for the 3D system [4][5], that understood as an area structure made lower input impedance ever GHz region. As a result, we can find which the input impedance is related largely with the DeCap TSV distribution pitch. Consideration of approach wiring to distributed DeCap TSVs is the key issue for the better PI performance as the result.