Wide bus chip-to-chip interconnection technology using fine pitch bump joint array for 3D LSI chip stacking

Abstract

We have developed a fabrication technology of fine-pitch cone shape Au bump array using nanoparticle deposition method for 3D LSI chip stacking. 1024-bit wide bus chip-to-chip interconnection circuit called Cool Interconnect has been also developed using fine-pitch bump joint array technology and precise flip chip bonding technology. Such a wide bus chip-to-chip interconnection is suitable instead of on-chip bus interconnection in multi-core architecture LSI system in order to achieve low power operation. We propose a testing approach to confirm the chip-to-chip interconnect electrical performance using scan path method and JTAG test method in 3D LSI chip stacking system. The preliminary data transmitting experiment of Cool Interconnect using designed, fabricated, and flip-chip stacked test LSI chips was successfully done under low power consumption with clock frequency of 50MHz.