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2008 Symposium on VLSI Technology最新文献

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Has the sun finally risen on photovoltaics? 光伏发电的太阳终于升起来了吗?
2008 Symposium on VLSI Technology Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159264
Mark Pinto
{"title":"Has the sun finally risen on photovoltaics?","authors":"Mark Pinto","doi":"10.1109/VTSA.2009.5159264","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159264","url":null,"abstract":"The idea of solar generated electricity dates to discovery of the photovoltaic (PV) effect in 1839 through to the first practical silicon solar cell in 1954. But even with concerns about oil and the environment, PV currently generates less than 0.1% of the worldpsilas electricity. We present here the case that PV is on the verge of becoming a major source of electrical power through a principle similar to that which underlies VLSI - the reduction of unit cost through nanomanufacturing.","PeriodicalId":173781,"journal":{"name":"2008 Symposium on VLSI Technology","volume":"26 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120814302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Novel 3-D structure for ultra high density flash memory with VRAT (Vertical-Recess-Array-Transistor) and PIPE (Planarized Integration on the same PlanE) 基于垂直凹槽阵列晶体管(VRAT)和PIPE(同一平面上的平面集成)的超高密度闪存新型三维结构
2008 Symposium on VLSI Technology Pub Date : 2008-06-17 DOI: 10.1109/VLSIT.2008.4588587
Jiyoung Kim, A. Hong, M. Ogawa, Siguang Ma, E. B. Song, You-Sheng Lin, Je-Woo Han, U. Chung, K. Wang
{"title":"Novel 3-D structure for ultra high density flash memory with VRAT (Vertical-Recess-Array-Transistor) and PIPE (Planarized Integration on the same PlanE)","authors":"Jiyoung Kim, A. Hong, M. Ogawa, Siguang Ma, E. B. Song, You-Sheng Lin, Je-Woo Han, U. Chung, K. Wang","doi":"10.1109/VLSIT.2008.4588587","DOIUrl":"https://doi.org/10.1109/VLSIT.2008.4588587","url":null,"abstract":"A 3-D flash memory cell of VRAT (vertical-recess-array-transistor) has been fabricated using a unique and simple 3-D integration method of PIPE (planarized integration on the same plane), which allows for the successful implementation of ultra high density flash memory. In addition, procedures to increase the memory density further using another advanced structure, Zigzag-VRAT (Z-VRAT), are developed.","PeriodicalId":173781,"journal":{"name":"2008 Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124274423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 41
Low Vt gate-first Al/TaN/[Ir3Si-HfSi2−x]/HfLaON CMOS using simple laser annealing/reflection 采用简单激光退火/反射的低Vt门优先Al/TaN/[Ir3Si-HfSi2−x]/HfLaON CMOS
2008 Symposium on VLSI Technology Pub Date : 2008-06-17 DOI: 10.1109/VLSIT.2008.4588614
C. Liao, A. Chin, N. Su, M. Li, S. Wang
{"title":"Low Vt gate-first Al/TaN/[Ir3Si-HfSi2−x]/HfLaON CMOS using simple laser annealing/reflection","authors":"C. Liao, A. Chin, N. Su, M. Li, S. Wang","doi":"10.1109/VLSIT.2008.4588614","DOIUrl":"https://doi.org/10.1109/VLSIT.2008.4588614","url":null,"abstract":"We report low V<sub>t</sub> Al/TaN/[Ir<sub>3</sub>Si-HfSi<sub>2-x</sub>]/HfLaON CMOS using simple laser annealing/reflection with self-aligned and gate-first process compatible with current VLSI. At 1.05 nm EOT, good phi<sub>m-eff</sub> of 5.04 and 4.24 eV, low V<sub>t</sub> of -0.16 and 0.13 V, high mobility of 85 and 209 cm<sup>2</sup>/Vs, and small 85degC BTI les40 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS.","PeriodicalId":173781,"journal":{"name":"2008 Symposium on VLSI Technology","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117139100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A novel CVD-SiBCN Low-K spacer technology for high-speed applications 用于高速应用的新型CVD-SiBCN低k隔离技术
2008 Symposium on VLSI Technology Pub Date : 2008-06-17 DOI: 10.1109/VLSIT.2008.4588581
C. Ko, T. Kuan, K. Zhang, G. Tsai, S. Seutter, C. Wu, T.J. Wang, C. Ye, H.W. Chen, C. Ge, K. Wu, W. Lee
{"title":"A novel CVD-SiBCN Low-K spacer technology for high-speed applications","authors":"C. Ko, T. Kuan, K. Zhang, G. Tsai, S. Seutter, C. Wu, T.J. Wang, C. Ye, H.W. Chen, C. Ge, K. Wu, W. Lee","doi":"10.1109/VLSIT.2008.4588581","DOIUrl":"https://doi.org/10.1109/VLSIT.2008.4588581","url":null,"abstract":"State-of-the-art low-K spacer technology featuring novel CVD-SiBCN material is demonstrated for the first time. A significant 20% CMOS ring speed enhancement is demonstrated with SiBCN (K=5.2) spacer, compared to Si3N4 (K=7.5) spacer, due to reduced fringing capacitance and enhanced strain effects by spacer-PSS and CESL techniques. Electron mobility is improved by 6% for long channel NMOS transistor and gm,max is increased by 11% for short 35 nm physical gate length NMOS using a preferable spacer structure that is comprised of a low stress SiBCN spacer on thin SiO2 liner and a final 600degC rapid thermal post-anneal. Superior GIDL and better gate leakage is obtained because low permittivity SiBCN alleviates gate-fringing field effects (GF effects), and device reliability is not adversely impacted by this new process.","PeriodicalId":173781,"journal":{"name":"2008 Symposium on VLSI Technology","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114888679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
TSNWFET for SRAM cell application: Performance variation and process dependency SRAM单元应用的TSNWFET:性能变化和过程依赖
2008 Symposium on VLSI Technology Pub Date : 2008-06-17 DOI: 10.1109/VLSIT.2008.4588555
S. Suk, Y. Yeoh, Ming Li, K. Yeo, S. Kim, Dong Won Kim, Donggun Park, Won-Seoung Lee
{"title":"TSNWFET for SRAM cell application: Performance variation and process dependency","authors":"S. Suk, Y. Yeoh, Ming Li, K. Yeo, S. Kim, Dong Won Kim, Donggun Park, Won-Seoung Lee","doi":"10.1109/VLSIT.2008.4588555","DOIUrl":"https://doi.org/10.1109/VLSIT.2008.4588555","url":null,"abstract":"ION is increased about 25 % with the width/height (W/H) of 12/24 nm nanowire (NW) in comparison with the W/H of 12/12 nm at VG-VTH = 1 V. With these results, we have successfully fabricated NW SRAM arrays with the W/H of 5/15 nm and LG of 40 nm for the first time. Static noise margin (SNM) of 325 mV is achieved at VD = 1 V. NW height and gate oxide thickness dependency of n-ch twin silicon nanowire MOSFET (TSNWFET) on device variations is investigated. Line edge roughness and size variation are more critical than random dopant fluctuation in TSNWFET.","PeriodicalId":173781,"journal":{"name":"2008 Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122335619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
5 nm gate length Nanowire-FETs and planar UTB-FETs with pure germanium source/drain stressors and laser-free Melt-Enhanced Dopant (MeltED) diffusion and activation technique 采用纯锗源/漏源应力源和无激光熔融增强掺杂剂扩散激活技术的5nm栅极长度纳米线场效应管和平面utb场效应管
2008 Symposium on VLSI Technology Pub Date : 2008-06-17 DOI: 10.1109/VLSIT.2008.4588554
T. Liow, K. Tan, R. Lee, M. Zhu, B.L.-H. Tan, G. Samudra, N. Balasubramanian, Y. Yeo
{"title":"5 nm gate length Nanowire-FETs and planar UTB-FETs with pure germanium source/drain stressors and laser-free Melt-Enhanced Dopant (MeltED) diffusion and activation technique","authors":"T. Liow, K. Tan, R. Lee, M. Zhu, B.L.-H. Tan, G. Samudra, N. Balasubramanian, Y. Yeo","doi":"10.1109/VLSIT.2008.4588554","DOIUrl":"https://doi.org/10.1109/VLSIT.2008.4588554","url":null,"abstract":"We report the first demonstration of pure Ge source/drain (S/D) stressors (un embedded) on the ultra-narrow or ultra-thin Si S/D regions of Nanowire-FETs and UTB-FETs, compressively straining the channels to provide up to ~100% IDsat enhancement. Devices with 5 nm gate lengths were fabricated. In addition, we report a novel Melt-Enhanced Dopant (MeltED) diffusion and activation technique to form embedded Ge S/D stressor in the S/D regions of nanowire-FETs, boosting the channel strain even further, and achieving ~125% IDsat enhancement.","PeriodicalId":173781,"journal":{"name":"2008 Symposium on VLSI Technology","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128712438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Three-dimensional stress engineering in FinFETs for mobility/on-current enhancement and gate current reduction 用于迁移率/导通电流增强和栅极电流减小的finfet三维应力工程
2008 Symposium on VLSI Technology Pub Date : 2008-06-17 DOI: 10.1109/VLSIT.2008.4588547
M. Saitoh, A. Kaneko, K. Okano, T. Kinoshita, S. Inaba, Y. Toyoshima, K. Uchida
{"title":"Three-dimensional stress engineering in FinFETs for mobility/on-current enhancement and gate current reduction","authors":"M. Saitoh, A. Kaneko, K. Okano, T. Kinoshita, S. Inaba, Y. Toyoshima, K. Uchida","doi":"10.1109/VLSIT.2008.4588547","DOIUrl":"https://doi.org/10.1109/VLSIT.2008.4588547","url":null,"abstract":"In this paper, the first systematic study of uniaxial stress effects on mobility (mu)/on-current (Ion) enhancement and gate current (Ig) reduction in FinFETs is described. We demonstrate for the first time that Ig of (110) side-surface pFinFETs is largely reduced by longitudinal compressive stress due to out-of-plane mass increase. (110) n/pFinFETs are superior to (100) FinFETs in terms of higher mu/Ion enhancement ratio by longitudinal strain and comparable/higher short-channel Idsat. Three-dimensional stress design in FinFETs including transverse and vertical stresses is proposed based on the understanding of stress effects beyond bulk piezoresistance.","PeriodicalId":173781,"journal":{"name":"2008 Symposium on VLSI Technology","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124679931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Guidelines to improve mobility performances and BTI reliability of advanced high-k/metal gate stacks 改进先进高k/金属栅极堆的移动性能和BTI可靠性的指南
2008 Symposium on VLSI Technology Pub Date : 2008-06-17 DOI: 10.1109/VLSIT.2008.4588567
X. Garros, M. Cassé, G. Reimbold, F. Martin, C. Leroux, A. Fanton, O. Renault, V. Cosnier, F. Boulanger
{"title":"Guidelines to improve mobility performances and BTI reliability of advanced high-k/metal gate stacks","authors":"X. Garros, M. Cassé, G. Reimbold, F. Martin, C. Leroux, A. Fanton, O. Renault, V. Cosnier, F. Boulanger","doi":"10.1109/VLSIT.2008.4588567","DOIUrl":"https://doi.org/10.1109/VLSIT.2008.4588567","url":null,"abstract":"A systematic study of mobility performances and BTI reliability was done in advanced dielectrics stacks. By reducing the oxide films thicknesses THKles2.5 nm, PBTI becomes generally very low and associated lifetimes are always over 10 years. By studying a large variety of dielectric stacks we also clearly demonstrate that mobility performances, interface defects Nit and NBTI reliability are strongly correlated. All are affected by nitrogen species N which is clearly identified as the main mobility killer when it reaches unintentionally the Si interface during the deposition of nitrided gates or the nitridation steps. However, by optimizing the gate stacks, excellent mobility performances, up to 100% universal mobility at Eeff=1 MV/cm, and reliability can be achieved.","PeriodicalId":173781,"journal":{"name":"2008 Symposium on VLSI Technology","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126501186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Enhanced endurance of dual-bit SONOS NVM cells using the GIDL read method 使用GIDL读取方法增强双位SONOS NVM单元的持久度
2008 Symposium on VLSI Technology Pub Date : 2008-06-17 DOI: 10.1109/VLSIT.2008.4588595
A. Padilla, Sunyeong Lee, D. Carlton, T. Liu
{"title":"Enhanced endurance of dual-bit SONOS NVM cells using the GIDL read method","authors":"A. Padilla, Sunyeong Lee, D. Carlton, T. Liu","doi":"10.1109/VLSIT.2008.4588595","DOIUrl":"https://doi.org/10.1109/VLSIT.2008.4588595","url":null,"abstract":"Gate-induced drain leakage (GIDL) current is demonstrated to be more sensitive to charge stored locally within the gate-dielectric stack, as compared with the transistor threshold voltage (VT). Thus the sensing of GIDL rather than VT is advantageous for dual-bit SONOS NVM cell read operation, not only because it mitigates the complementary-bit disturb (CBD) issue and hence facilitates gate-length scaling, but also because it allows for reductions in stored charge and hence lower program/erase voltages for improved endurance.","PeriodicalId":173781,"journal":{"name":"2008 Symposium on VLSI Technology","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134517293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Strain enhanced low-VT CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay 应变增强低vt CMOS，具有La/ al掺杂HfSiO/TaC和10ps逆变器延迟
2008 Symposium on VLSI Technology Pub Date : 2008-06-17 DOI: 10.1109/VLSIT.2008.4588590
S. Kubicek, T. Schram, E. Rohr, V. Paraschiv, R. Vos, M. Demand, C. Adelmann, T. Witters, L. Nyns, A. Delabie, L. Ragnarsson, T. Chiarella, C. Kerner, A. Mercha, B. Parvais, M. Aoulaiche, C. Ortolland, H. Yu, A. Veloso, L. Witters, R. Singanamalla, T. Kauerauf, S. Brus, C. Vrancken, V. Chang, S. Chang, R. Mitsuhashi, Y. Okuno, A. Akheyar, H. Cho, J. Hooker, B. O’Sullivan, S. Van Elshocht, K. De Meyer, M. Jurczak, P. Absil, S. Biesemans, T. Hoffmann
{"title":"Strain enhanced low-VT CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay","authors":"S. Kubicek, T. Schram, E. Rohr, V. Paraschiv, R. Vos, M. Demand, C. Adelmann, T. Witters, L. Nyns, A. Delabie, L. Ragnarsson, T. Chiarella, C. Kerner, A. Mercha, B. Parvais, M. Aoulaiche, C. Ortolland, H. Yu, A. Veloso, L. Witters, R. Singanamalla, T. Kauerauf, S. Brus, C. Vrancken, V. Chang, S. Chang, R. Mitsuhashi, Y. Okuno, A. Akheyar, H. Cho, J. Hooker, B. O’Sullivan, S. Van Elshocht, K. De Meyer, M. Jurczak, P. Absil, S. Biesemans, T. Hoffmann","doi":"10.1109/VLSIT.2008.4588590","DOIUrl":"https://doi.org/10.1109/VLSIT.2008.4588590","url":null,"abstract":"We discuss several advancements over our previous report (S. Kubicek, 2006): - Introduction of conventional stress boosters resulting in 16% and 11% for nMOS and pMOS respectively. For the first time the compatibility of SMT (stress memorization technique) with high-kappa/metal gate is demonstrated. In addition, we developed a blanket SMT process that does not require a photo to protect the pMOS by selecting a hydrogen-rich SiN film. - A comprehensive study of HfSiO and HfO2 as function of La/Al doping and spike/laser annealing. Parameters studied include Vt tuning, reliability and process control. - Demonstration of fast invertor delay of 10 ps including high frequency response analysis revealing the negative impact of high metal sheet resistance and parasitic metal-poly interface oxide.","PeriodicalId":173781,"journal":{"name":"2008 Symposium on VLSI Technology","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131494411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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