S. Kubicek, T. Schram, E. Rohr, V. Paraschiv, R. Vos, M. Demand, C. Adelmann, T. Witters, L. Nyns, A. Delabie, L. Ragnarsson, T. Chiarella, C. Kerner, A. Mercha, B. Parvais, M. Aoulaiche, C. Ortolland, H. Yu, A. Veloso, L. Witters, R. Singanamalla, T. Kauerauf, S. Brus, C. Vrancken, V. Chang, S. Chang, R. Mitsuhashi, Y. Okuno, A. Akheyar, H. Cho, J. Hooker, B. O’Sullivan, S. Van Elshocht, K. De Meyer, M. Jurczak, P. Absil, S. Biesemans, T. Hoffmann
{"title":"应变增强低vt CMOS，具有La/ al掺杂HfSiO/TaC和10ps逆变器延迟","authors":"S. Kubicek, T. Schram, E. Rohr, V. Paraschiv, R. Vos, M. Demand, C. Adelmann, T. Witters, L. Nyns, A. Delabie, L. Ragnarsson, T. Chiarella, C. Kerner, A. Mercha, B. Parvais, M. Aoulaiche, C. Ortolland, H. Yu, A. Veloso, L. Witters, R. Singanamalla, T. Kauerauf, S. Brus, C. Vrancken, V. Chang, S. Chang, R. Mitsuhashi, Y. Okuno, A. Akheyar, H. Cho, J. Hooker, B. O’Sullivan, S. Van Elshocht, K. De Meyer, M. Jurczak, P. Absil, S. Biesemans, T. Hoffmann","doi":"10.1109/VLSIT.2008.4588590","DOIUrl":null,"url":null,"abstract":"We discuss several advancements over our previous report (S. Kubicek, 2006): - Introduction of conventional stress boosters resulting in 16% and 11% for nMOS and pMOS respectively. For the first time the compatibility of SMT (stress memorization technique) with high-kappa/metal gate is demonstrated. In addition, we developed a blanket SMT process that does not require a photo to protect the pMOS by selecting a hydrogen-rich SiN film. - A comprehensive study of HfSiO and HfO2 as function of La/Al doping and spike/laser annealing. Parameters studied include Vt tuning, reliability and process control. - Demonstration of fast invertor delay of 10 ps including high frequency response analysis revealing the negative impact of high metal sheet resistance and parasitic metal-poly interface oxide.","PeriodicalId":173781,"journal":{"name":"2008 Symposium on VLSI Technology","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Strain enhanced low-VT CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay\",\"authors\":\"S. Kubicek, T. Schram, E. Rohr, V. Paraschiv, R. Vos, M. Demand, C. Adelmann, T. Witters, L. Nyns, A. Delabie, L. Ragnarsson, T. Chiarella, C. Kerner, A. Mercha, B. Parvais, M. Aoulaiche, C. Ortolland, H. Yu, A. Veloso, L. Witters, R. Singanamalla, T. Kauerauf, S. Brus, C. Vrancken, V. Chang, S. Chang, R. Mitsuhashi, Y. Okuno, A. Akheyar, H. Cho, J. Hooker, B. O’Sullivan, S. Van Elshocht, K. De Meyer, M. Jurczak, P. Absil, S. Biesemans, T. Hoffmann\",\"doi\":\"10.1109/VLSIT.2008.4588590\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We discuss several advancements over our previous report (S. Kubicek, 2006): - Introduction of conventional stress boosters resulting in 16% and 11% for nMOS and pMOS respectively. For the first time the compatibility of SMT (stress memorization technique) with high-kappa/metal gate is demonstrated. In addition, we developed a blanket SMT process that does not require a photo to protect the pMOS by selecting a hydrogen-rich SiN film. - A comprehensive study of HfSiO and HfO2 as function of La/Al doping and spike/laser annealing. Parameters studied include Vt tuning, reliability and process control. - Demonstration of fast invertor delay of 10 ps including high frequency response analysis revealing the negative impact of high metal sheet resistance and parasitic metal-poly interface oxide.\",\"PeriodicalId\":173781,\"journal\":{\"name\":\"2008 Symposium on VLSI Technology\",\"volume\":\"31 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-06-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2008.4588590\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2008.4588590","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
We discuss several advancements over our previous report (S. Kubicek, 2006): - Introduction of conventional stress boosters resulting in 16% and 11% for nMOS and pMOS respectively. For the first time the compatibility of SMT (stress memorization technique) with high-kappa/metal gate is demonstrated. In addition, we developed a blanket SMT process that does not require a photo to protect the pMOS by selecting a hydrogen-rich SiN film. - A comprehensive study of HfSiO and HfO2 as function of La/Al doping and spike/laser annealing. Parameters studied include Vt tuning, reliability and process control. - Demonstration of fast invertor delay of 10 ps including high frequency response analysis revealing the negative impact of high metal sheet resistance and parasitic metal-poly interface oxide.
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