5 nm gate length Nanowire-FETs and planar UTB-FETs with pure germanium source/drain stressors and laser-free Melt-Enhanced Dopant (MeltED) diffusion and activation technique
T. Liow, K. Tan, R. Lee, M. Zhu, B.L.-H. Tan, G. Samudra, N. Balasubramanian, Y. Yeo
{"title":"5 nm gate length Nanowire-FETs and planar UTB-FETs with pure germanium source/drain stressors and laser-free Melt-Enhanced Dopant (MeltED) diffusion and activation technique","authors":"T. Liow, K. Tan, R. Lee, M. Zhu, B.L.-H. Tan, G. Samudra, N. Balasubramanian, Y. Yeo","doi":"10.1109/VLSIT.2008.4588554","DOIUrl":null,"url":null,"abstract":"We report the first demonstration of pure Ge source/drain (S/D) stressors (un embedded) on the ultra-narrow or ultra-thin Si S/D regions of Nanowire-FETs and UTB-FETs, compressively straining the channels to provide up to ~100% IDsat enhancement. Devices with 5 nm gate lengths were fabricated. In addition, we report a novel Melt-Enhanced Dopant (MeltED) diffusion and activation technique to form embedded Ge S/D stressor in the S/D regions of nanowire-FETs, boosting the channel strain even further, and achieving ~125% IDsat enhancement.","PeriodicalId":173781,"journal":{"name":"2008 Symposium on VLSI Technology","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"18","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2008.4588554","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 18
Abstract
We report the first demonstration of pure Ge source/drain (S/D) stressors (un embedded) on the ultra-narrow or ultra-thin Si S/D regions of Nanowire-FETs and UTB-FETs, compressively straining the channels to provide up to ~100% IDsat enhancement. Devices with 5 nm gate lengths were fabricated. In addition, we report a novel Melt-Enhanced Dopant (MeltED) diffusion and activation technique to form embedded Ge S/D stressor in the S/D regions of nanowire-FETs, boosting the channel strain even further, and achieving ~125% IDsat enhancement.