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Two-bit cell operation in diode-switch phase change memory cells with 90nm technology 采用90nm技术的二极管开关相变存储单元的两位单元操作
2008 Symposium on VLSI Technology Pub Date : 2008-06-17 DOI: 10.1109/VLSIT.2008.4588577
D. Kang, J. H. Lee, J. Kong, Dae-Won Ha, J. Yu, C. Y. Um, Joon-Min Park, F. Yeung, Jedon Kim, Woon Ik Park, Y. J. Jeon, Mi-Hyang Lee, Yun-Heub Song, Jae-joon Oh, G. Jeong, H.G. Jeong
{"title":"Two-bit cell operation in diode-switch phase change memory cells with 90nm technology","authors":"D. Kang, J. H. Lee, J. Kong, Dae-Won Ha, J. Yu, C. Y. Um, Joon-Min Park, F. Yeung, Jedon Kim, Woon Ik Park, Y. J. Jeon, Mi-Hyang Lee, Yun-Heub Song, Jae-joon Oh, G. Jeong, H.G. Jeong","doi":"10.1109/VLSIT.2008.4588577","DOIUrl":"https://doi.org/10.1109/VLSIT.2008.4588577","url":null,"abstract":"This paper firstly reports key factors which are to be necessarily considered for the successful two-bit (four-level) cell operation in a phase-change random access memory (PRAM). They are: 1) the write-and-verify (WAV) writing of four-level resistance states; and 2) the moderate-quenched (MQ) writing of intermediate resistance levels, 3) the optimization of temporal resistance increase (so-called resistance drift) and 4) of resistance increase after thermal annealing. With taking into account of them, we realized a two-bit cell operation in diode-switch phase change memory cells with 90 nm technology. All of four resistance levels are highly write endurable and immune to write disturbance above 108 cycles, respectively. In addition, they are non-destructively readable above 107 read pulses at 100 ns and 1 uA.","PeriodicalId":173781,"journal":{"name":"2008 Symposium on VLSI Technology","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130704025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 92
A scaled floating body cell (FBC) memory with high-k+metal gate on thin-silicon and thin-BOX for 16-nm technology node and beyond 一种适用于16nm及以上技术节点的基于薄硅和薄盒的高k+金属栅极的规模化浮体电池(FBC)存储器
2008 Symposium on VLSI Technology Pub Date : 2008-06-17 DOI: 10.1109/VLSIT.2008.4588575
I. Ban, U. Avci, D. Kencke, P. Chang
{"title":"A scaled floating body cell (FBC) memory with high-k+metal gate on thin-silicon and thin-BOX for 16-nm technology node and beyond","authors":"I. Ban, U. Avci, D. Kencke, P. Chang","doi":"10.1109/VLSIT.2008.4588575","DOIUrl":"https://doi.org/10.1109/VLSIT.2008.4588575","url":null,"abstract":"A scaled, undoped, thin-BOX, planar FBC technology is demonstrated for the first time, featuring 10-nm BOX, 25-nm SOI, high-k, metal gate, separate back-gate (BG) doping, and raised source-drain epitaxy. Retention of a minimum 3-muA sensing window for 100 ms, in devices with 60-nm gate-length (Lg) and 70-nm diffusion width (W), represents the best retention time of all sub-100-nm FBC devices. FBC scaling is predicted to be feasible at least to 40-nm Lg, enabling memory cell sizes much smaller than 6T-SRAM at 16-nm technology node. Functional 32-nm Lg devices suggest the feasibility at the 11-nm technology node.","PeriodicalId":173781,"journal":{"name":"2008 Symposium on VLSI Technology","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133865879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
New global shutter CMOS imager with 2 transistors per pixel 新的全局快门CMOS成像仪，每像素2个晶体管
2008 Symposium on VLSI Technology Pub Date : 2008-06-17 DOI: 10.1109/VLSIT.2008.4588616
M. Funaki, T. Shimizu, S. Orihara, H. kawanaka, M. Kurihara, H. Sato, N. Katsumata, M. Oikawa, J. Higuchi, K. Oe, R. Kuga, K. Maki, T. Nishibata
{"title":"New global shutter CMOS imager with 2 transistors per pixel","authors":"M. Funaki, T. Shimizu, S. Orihara, H. kawanaka, M. Kurihara, H. Sato, N. Katsumata, M. Oikawa, J. Higuchi, K. Oe, R. Kuga, K. Maki, T. Nishibata","doi":"10.1109/VLSIT.2008.4588616","DOIUrl":"https://doi.org/10.1109/VLSIT.2008.4588616","url":null,"abstract":"We present a new global shutter CMOS imager with 2 transistors per pixel. The first transistor is a ring gate transistor for accumulating holes that modulate threshold voltage. The second one is a transfer gate transistor that transfers holes from a PD to the ring gate transistor at the same time in all pixels. Simple structure allows us to realize 5.4 um pixel pitch, kTC noise free, and global shutter sensor using 0.35 um technology.","PeriodicalId":173781,"journal":{"name":"2008 Symposium on VLSI Technology","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130969845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Embedded split-gate flash memory with silicon nanocrystals for 90nm and beyond 嵌入式分栅闪存与硅纳米晶体为90纳米及以上
2008 Symposium on VLSI Technology Pub Date : 2008-06-17 DOI: 10.1109/VLSIT.2008.4588592
G. Chindalore, J. Yater, H. Gasquet, M. Suhail, S. Kang, C. Hong, N. Ellis, G. Rinkenberger, J. Shen, M. Herrick, W. Malloch, R. Syzdek, K. Baker, Ko-Min Chang
{"title":"Embedded split-gate flash memory with silicon nanocrystals for 90nm and beyond","authors":"G. Chindalore, J. Yater, H. Gasquet, M. Suhail, S. Kang, C. Hong, N. Ellis, G. Rinkenberger, J. Shen, M. Herrick, W. Malloch, R. Syzdek, K. Baker, Ko-Min Chang","doi":"10.1109/VLSIT.2008.4588592","DOIUrl":"https://doi.org/10.1109/VLSIT.2008.4588592","url":null,"abstract":"We present a split-gate based NOR flash memory array with silicon nanocrystals as the storage medium. 128 KB memory arrays have been evaluated with this technology and the results presented here show a nanocrystal memory that has been demonstrated to achieve a minimum 1.5 V operating window that is maintained through 10 K program/erase cycles; well controlled array threshold distributions; fast source-side injection programming (10-20 us); fast tunnel erase into the gate; and robust high temperature data retention for both uncycled and cycled arrays. Results presented here with focus on the array operation demonstrate the maturity of this technology for implementation into consumer, industrial, and automotive microcontrollers.","PeriodicalId":173781,"journal":{"name":"2008 Symposium on VLSI Technology","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131043972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Cost-effective Ni-melt-FUSI boosting 32-nm node LSTP transistors 性价比高的Ni-melt-FUSI助推32nm节点LSTP晶体管
2008 Symposium on VLSI Technology Pub Date : 2008-06-17 DOI: 10.1109/VLSIT.2008.4588598
H. Fukutome, K. Kawamura, H. Ohta, K. Hosaka, T. Sakoda, Y. Morisaki, Y. Momiyama
{"title":"Cost-effective Ni-melt-FUSI boosting 32-nm node LSTP transistors","authors":"H. Fukutome, K. Kawamura, H. Ohta, K. Hosaka, T. Sakoda, Y. Morisaki, Y. Momiyama","doi":"10.1109/VLSIT.2008.4588598","DOIUrl":"https://doi.org/10.1109/VLSIT.2008.4588598","url":null,"abstract":"We demonstrated for the first time that novel Ni-FUSI process using FLA (Melt-FUSI) dramatically improved both electrical characteristics and cost-benefit performance of LSTP devices. Since the T<sub>inv</sub> was aggressively scaled (T<sub>inv</sub> = 2.1 nm) with keeping SiON-gate leakage current and increasing hole mobility twice, we achieved the record I<sub>on</sub> of 300 muA/mum at the I<sub>off</sub> of 20 pA/mum for the pMOS transistor with the L<sub>g</sub> of 45 nm at V<sub>d</sub> of -1.2 V.","PeriodicalId":173781,"journal":{"name":"2008 Symposium on VLSI Technology","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134434101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A novel junction-free BE-SONOS NAND flash 一种新型无结BE-SONOS NAND闪存
2008 Symposium on VLSI Technology Pub Date : 2008-06-17 DOI: 10.1109/VLSIT.2008.4588594
H. Lue, E. Lai, Y. Hsiao, S. Hong, M.T. Wu, F. Hsu, N. Z. Lien, S.Y. Wang, L.W. Yang, T. Yang, K.C. Chen, K. Hsieh, R. Liu, Chih-Yuan Lu
{"title":"A novel junction-free BE-SONOS NAND flash","authors":"H. Lue, E. Lai, Y. Hsiao, S. Hong, M.T. Wu, F. Hsu, N. Z. Lien, S.Y. Wang, L.W. Yang, T. Yang, K.C. Chen, K. Hsieh, R. Liu, Chih-Yuan Lu","doi":"10.1109/VLSIT.2008.4588594","DOIUrl":"https://doi.org/10.1109/VLSIT.2008.4588594","url":null,"abstract":"We have successfully demonstrated a novel junction-free BE-SONOS NAND Flash. Junction-free devices greatly improve the short channel effect and thus promise scaling of NAND Flash below 20 nm node. Instead of S/D junctions a very small space (Lt 30 nm) is left between adjacent devices. Junction is formed only at the outer region of NAND array, while there is no junction inside the array. Fringe field from the gate inverts the Si under the narrow space allowing conduction without a diffusion junction. Successful n-channel, p-channel and TFT BE-SONOS NAND devices are demonstrated using this technique. Simulation results suggest that this novel junction-free technique is scalable beyond 20 nm node. Moreover, the junction-free devices are unaffected by the thermal budget in the 3D TFT devices. This new device can be implemented in the current NAND Flash process without introducing new masks.","PeriodicalId":173781,"journal":{"name":"2008 Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129671982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Single metal/single dielectric gate stack realizing triple effective workfunction for embedded memory application 单金属/单介质栅极堆叠，实现嵌入式存储器应用的三重有效工作功能
2008 Symposium on VLSI Technology Pub Date : 2008-06-17 DOI: 10.1109/VLSIT.2008.4588558
K. Manabe, K. Masuzaki, T. Ogura, T. Nakagawa, M. Saitoh, H. Sunamura, T. Tatsumi, H. Watanabe
{"title":"Single metal/single dielectric gate stack realizing triple effective workfunction for embedded memory application","authors":"K. Manabe, K. Masuzaki, T. Ogura, T. Nakagawa, M. Saitoh, H. Sunamura, T. Tatsumi, H. Watanabe","doi":"10.1109/VLSIT.2008.4588558","DOIUrl":"https://doi.org/10.1109/VLSIT.2008.4588558","url":null,"abstract":"We demonstrate midgap and band-edge effective workfunctions (EWFs) control with simple metal gate process scheme (single metal gate/single gate dielectric), using impurity-segregated NiSi2/SiON structure for embedded memory application. The application of midgap and band-edge EWF enables us to lower power consumption in SRAM and logic devices by 30% and 15% compared to poly-Si devices, respectively, due to reduced channel impurity concentration, suppressed gate depletion and high carrier mobility. These results show that NiSi2/SiON stack is one of the most promising candidates for future system on chip (SoC) devices with embedded memory.","PeriodicalId":173781,"journal":{"name":"2008 Symposium on VLSI Technology","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128491790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process 具有成本效益的32nm高k /金属栅极CMOS技术，适用于单金属/栅极优先工艺的低功耗应用
2008 Symposium on VLSI Technology Pub Date : 2008-06-17 DOI: 10.1109/VLSIT.2008.4588573
X. Chen, S. Samavedam, V. Narayanan, K. Stein, C. Hobbs, C. Baiocco, W. Li, D. Jaeger, M. Zaleski, H.S. Yang, N. Kim, Y. Lee, D. Zhang, L. Kang, J. Chen, H. Zhuang, A. Sheikh, J. Wallner, M. Aquilino, J. Han, Z. Jin, J. Li, G. Massey, S. Kalpat, R. Jha, N. Moumen, R. Mo, S. Kirshnan, X. Wang, M. Chudzik, M. Chowdhury, D. Nair, C. Reddy, Y. Teh, C. Kothandaraman, D. Coolbaugh, S. Pandey, D. Tekleab, A. Thean, M. Sherony, C. Lage, J. Sudijono, R. Lindsay, J. Ku, M. Khare, A. Steegen
{"title":"A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process","authors":"X. Chen, S. Samavedam, V. Narayanan, K. Stein, C. Hobbs, C. Baiocco, W. Li, D. Jaeger, M. Zaleski, H.S. Yang, N. Kim, Y. Lee, D. Zhang, L. Kang, J. Chen, H. Zhuang, A. Sheikh, J. Wallner, M. Aquilino, J. Han, Z. Jin, J. Li, G. Massey, S. Kalpat, R. Jha, N. Moumen, R. Mo, S. Kirshnan, X. Wang, M. Chudzik, M. Chowdhury, D. Nair, C. Reddy, Y. Teh, C. Kothandaraman, D. Coolbaugh, S. Pandey, D. Tekleab, A. Thean, M. Sherony, C. Lage, J. Sudijono, R. Lindsay, J. Ku, M. Khare, A. Steegen","doi":"10.1109/VLSIT.2008.4588573","DOIUrl":"https://doi.org/10.1109/VLSIT.2008.4588573","url":null,"abstract":"For the first time, we have demonstrated a 32 nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mum2. Record NMOS/PMOS drive currents of 1000/575 muA/mum, respectively, have been achieved at 1 nA/mum off-current and 1.1 V Vdd with a low cost process. With this high performance transistor, Vdd can be further scaled to 1.0 V for active power reduction. Through aggressive EOT scaling and band-edge work-function metal gate stacks, appropriate Vts and superior short channel control has been achieved for both NMOS and PMOS at Lgate = 30 nm. Compared to SiON-Poly, 30% RO delay reduction has been demonstrated with HK-MG devices. 40% Vt mismatch reduction has been shown with the Tinv scaling. Furthermore, it has been shown that the 1/f noise and transistor reliability exceed the technology requirements.","PeriodicalId":173781,"journal":{"name":"2008 Symposium on VLSI Technology","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126613214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 111
Gate-all-around single silicon nanowire MOSFET with 7 nm width for SONOS NAND flash memory 门全能单硅纳米线MOSFET，宽度为7nm，用于SONOS NAND闪存
2008 Symposium on VLSI Technology Pub Date : 2008-06-01 DOI: 10.1109/VLSIT.2008.4588593
K. Yeo, K. Cho, Ming Li, S. Suk, Y. Yeoh, Min-Sang Kim, H. Bae, Ji-myoung Lee, Suk-kang Sung, Jun Seo, Bokkyoung Park, Dong-Won Kim, Donggun Park, Won-Seoung Lee
{"title":"Gate-all-around single silicon nanowire MOSFET with 7 nm width for SONOS NAND flash memory","authors":"K. Yeo, K. Cho, Ming Li, S. Suk, Y. Yeoh, Min-Sang Kim, H. Bae, Ji-myoung Lee, Suk-kang Sung, Jun Seo, Bokkyoung Park, Dong-Won Kim, Donggun Park, Won-Seoung Lee","doi":"10.1109/VLSIT.2008.4588593","DOIUrl":"https://doi.org/10.1109/VLSIT.2008.4588593","url":null,"abstract":"Gate-all-around (GAA) MOSFET with single silicon nanowire is fabricated and applied to SONOS memory as a cell transistor for NAND flash string. Driving current over 1 uA, which is sufficient to NAND string, is obtained with single nanowire of ~7 nm width. Using FN tunneling conditions, VTH window of 4.5 V and fast program/erase (P/E) speed of ~10 us are obtained, respectively. The smaller nanowire width is, the faster program speed and the larger VTH shift are achieved. P/E operations in NAND string with GAA SONOS nanowire are demonstrated for the first time.","PeriodicalId":173781,"journal":{"name":"2008 Symposium on VLSI Technology","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133393333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
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