H. Lue, E. Lai, Y. Hsiao, S. Hong, M.T. Wu, F. Hsu, N. Z. Lien, S.Y. Wang, L.W. Yang, T. Yang, K.C. Chen, K. Hsieh, R. Liu, Chih-Yuan Lu
{"title":"一种新型无结BE-SONOS NAND闪存","authors":"H. Lue, E. Lai, Y. Hsiao, S. Hong, M.T. Wu, F. Hsu, N. Z. Lien, S.Y. Wang, L.W. Yang, T. Yang, K.C. Chen, K. Hsieh, R. Liu, Chih-Yuan Lu","doi":"10.1109/VLSIT.2008.4588594","DOIUrl":null,"url":null,"abstract":"We have successfully demonstrated a novel junction-free BE-SONOS NAND Flash. Junction-free devices greatly improve the short channel effect and thus promise scaling of NAND Flash below 20 nm node. Instead of S/D junctions a very small space (Lt 30 nm) is left between adjacent devices. Junction is formed only at the outer region of NAND array, while there is no junction inside the array. Fringe field from the gate inverts the Si under the narrow space allowing conduction without a diffusion junction. Successful n-channel, p-channel and TFT BE-SONOS NAND devices are demonstrated using this technique. Simulation results suggest that this novel junction-free technique is scalable beyond 20 nm node. Moreover, the junction-free devices are unaffected by the thermal budget in the 3D TFT devices. This new device can be implemented in the current NAND Flash process without introducing new masks.","PeriodicalId":173781,"journal":{"name":"2008 Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"20","resultStr":"{\"title\":\"A novel junction-free BE-SONOS NAND flash\",\"authors\":\"H. Lue, E. Lai, Y. Hsiao, S. Hong, M.T. Wu, F. Hsu, N. Z. Lien, S.Y. Wang, L.W. Yang, T. Yang, K.C. Chen, K. Hsieh, R. Liu, Chih-Yuan Lu\",\"doi\":\"10.1109/VLSIT.2008.4588594\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We have successfully demonstrated a novel junction-free BE-SONOS NAND Flash. Junction-free devices greatly improve the short channel effect and thus promise scaling of NAND Flash below 20 nm node. Instead of S/D junctions a very small space (Lt 30 nm) is left between adjacent devices. Junction is formed only at the outer region of NAND array, while there is no junction inside the array. Fringe field from the gate inverts the Si under the narrow space allowing conduction without a diffusion junction. Successful n-channel, p-channel and TFT BE-SONOS NAND devices are demonstrated using this technique. Simulation results suggest that this novel junction-free technique is scalable beyond 20 nm node. Moreover, the junction-free devices are unaffected by the thermal budget in the 3D TFT devices. This new device can be implemented in the current NAND Flash process without introducing new masks.\",\"PeriodicalId\":173781,\"journal\":{\"name\":\"2008 Symposium on VLSI Technology\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-06-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"20\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2008.4588594\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2008.4588594","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
We have successfully demonstrated a novel junction-free BE-SONOS NAND Flash. Junction-free devices greatly improve the short channel effect and thus promise scaling of NAND Flash below 20 nm node. Instead of S/D junctions a very small space (Lt 30 nm) is left between adjacent devices. Junction is formed only at the outer region of NAND array, while there is no junction inside the array. Fringe field from the gate inverts the Si under the narrow space allowing conduction without a diffusion junction. Successful n-channel, p-channel and TFT BE-SONOS NAND devices are demonstrated using this technique. Simulation results suggest that this novel junction-free technique is scalable beyond 20 nm node. Moreover, the junction-free devices are unaffected by the thermal budget in the 3D TFT devices. This new device can be implemented in the current NAND Flash process without introducing new masks.