Hyunjin Lee, Dae-Young Kim, B. Choi, G. Cho, Sungwoong Chung, Wan-Soo Kim, M. Chang, Young-Sik Kim, Junki Kim, Taekwan Kim, Hyung-Hwan Kim, Haejung Lee, Han-Sang Song, Sung-Kye Park, Jin-Woong Kim, Sung-Joo Hong, Sung-Wook Park
{"title":"Fully integrated and functioned 44nm DRAM technology for 1GB DRAM","authors":"Hyunjin Lee, Dae-Young Kim, B. Choi, G. Cho, Sungwoong Chung, Wan-Soo Kim, M. Chang, Young-Sik Kim, Junki Kim, Taekwan Kim, Hyung-Hwan Kim, Haejung Lee, Han-Sang Song, Sung-Kye Park, Jin-Woong Kim, Sung-Joo Hong, Sung-Wook Park","doi":"10.1109/VLSIT.2008.4588572","DOIUrl":"https://doi.org/10.1109/VLSIT.2008.4588572","url":null,"abstract":"44 nm feature sized 8F2 1Gb DRAM is fully integrated and functioned for the first time with the smallest cell size of 0.015 um2. A novel cell-transistor structure and new DRAM process technologies are developed. In order to control the threshold voltage uniformity and body-bias sensitivity of saddle-fin cell-transistor, the channel doping profile and saddle-fin geometric dependency were analytically expressed with experimental data. The weak fin height dependency on cell-VT diminishes the burden of the saddle-fin patterning processes. And the low body-bias sensitivity of the saddle-fin cell-transistor leads wide tWR (write recovery time) margins. Cylinder-like MIM cell capacitor with ZAZ dielectric is exploited on cell capacitor. Copper implemented triple-metal layer and WN barrier-metal techniques were developed to decrease chip size.","PeriodicalId":173781,"journal":{"name":"2008 Symposium on VLSI Technology","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121675871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"32nm device architecture optimization for critical path speed improvement","authors":"R. Gwoziecki, S. Kohler, F. Arnaud","doi":"10.1109/VLSIT.2008.4588610","DOIUrl":"https://doi.org/10.1109/VLSIT.2008.4588610","url":null,"abstract":"This study investigates key elements improving CMOS critical path speed. We proposed a full analysis of input signal slope impact on the switching current trajectories depending on Vt centering. Based on inverter output characteristics shape, we demonstrated that speed of low-Vt (LVT) path preferred higher drive current (ION) whereas high-Vt (HVT) cells speed is enhanced by lower drain induced barrier lowering (DIBL). Finally, we proposed a link with transistor architecture by optimizing halos and light-doping-drain (LDD) design to improve logic gate as a function of Vt options.","PeriodicalId":173781,"journal":{"name":"2008 Symposium on VLSI Technology","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132576448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Mizuno, Y. Moriyama, T. Tezuka, N. Sugiyama, S. Takagi
{"title":"Experimental study of single source-heterojunction MOS transistors (SHOTs) under quasi-ballistic transport","authors":"T. Mizuno, Y. Moriyama, T. Tezuka, N. Sugiyama, S. Takagi","doi":"10.1109/VLSIT.2008.4588548","DOIUrl":"https://doi.org/10.1109/VLSIT.2008.4588548","url":null,"abstract":"In this study, we have experimentally demonstrated the high performance of the single source heterojunction MOSFETs (SHOTs) without the energy spike of the drain heterojuction. We have studied the influence of the drain energy spike on the MOSFET performance. Moreover, we have clarified the physical mechanism for the high velocity electron injection in SHOTs, through the lattice temperature dependence of the electron velocity, comparing with that of strained-SOIs (SSOIs).","PeriodicalId":173781,"journal":{"name":"2008 Symposium on VLSI Technology","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132198427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Morita, R. Tsuchiya, T. Ishigaki, N. Sugii, T. Iwamatsu, T. Ipposhi, H. Oda, Y. Inoue, K. Torii, S. Kimura
{"title":"Smallest Vth variability achieved by intrinsic silicon on thin BOX (SOTB) CMOS with single metal gate","authors":"Y. Morita, R. Tsuchiya, T. Ishigaki, N. Sugii, T. Iwamatsu, T. Ipposhi, H. Oda, Y. Inoue, K. Torii, S. Kimura","doi":"10.1109/VLSIT.2008.4588604","DOIUrl":"https://doi.org/10.1109/VLSIT.2008.4588604","url":null,"abstract":"A ldquosilicon on thin BOXrdquo (SOTB) CMOS with a 50-nm single metal (FUSI) gate has been developed. By employing an intrinsic channel and a metal gate, this SOTB achieves the smallest Vth variability ever reported. The measured Pelgrom coefficients of the SOTB were 1.8 and 1.5 for NMOS and PMOS, respectively, even in the case of relatively thick EOT of 1.9 nm. Both multi-Vth control as well as suppression of short-channel effects were carried out simply by adjusting the impurity concentration beneath the BOX layer while keeping the channel almost intrinsic. Inverter delay and off-current were optimized by controlling gate-overlap length by means of a dual-layer offset spacer. It is shown that, within planar-type low-power CMOS devices, the SOTB is the most scalable because of its capability of multi-Vth and excellent matching characteristics.","PeriodicalId":173781,"journal":{"name":"2008 Symposium on VLSI Technology","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123597262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Ortolland, T. Noda, T. Chiarella, S. Kubicek, C. Kerner, W. Vandervorst, A. Opdebeeck, C. Vrancken, N. Horiguchi, M. de Potter, M. Aoulaiche, E. Rosseel, S. Felch, P. Absil, R. Schreutelkamp, S. Biesemans, T. Hoffmann
{"title":"Laser-annealed junctions with advanced CMOS gate stacks for 32nm Node: Perspectives on device performance and manufacturability","authors":"C. Ortolland, T. Noda, T. Chiarella, S. Kubicek, C. Kerner, W. Vandervorst, A. Opdebeeck, C. Vrancken, N. Horiguchi, M. de Potter, M. Aoulaiche, E. Rosseel, S. Felch, P. Absil, R. Schreutelkamp, S. Biesemans, T. Hoffmann","doi":"10.1109/VLSIT.2008.4588612","DOIUrl":"https://doi.org/10.1109/VLSIT.2008.4588612","url":null,"abstract":"In this paper, we report on the integration of laser-annealed junctions into a state-of-the-art high-k/metal gate process flow. After implant optimization, we achieve excellent Lg scaling of 15/30 nm over a spike reference, for nMOS and pMOS respectively, without any performance loss. This enables to fabricate transistors with Lgmin meeting the 32 nm node requirement. In addition, we highlight the implication of the metal gate integration flow (ldquogate-firstrdquo vs. ldquogate-lastrdquo) on the junctions design. Also, we demonstrate that a millisecond anneal only (MSA-only) process can fulfill even the stringent junction leakage requirement for low power applications. Finally, based on a combination of physical and electrical characterization, we show for the very first time that micro-uniformities specific to this diffusion-less process have a negligible electrical impact in nominal devices.","PeriodicalId":173781,"journal":{"name":"2008 Symposium on VLSI Technology","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116360612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Lue, T. Hsu, S. Lai, Y. Hsiao, W.C. Peng, C.W. Liao, Y. Huang, S. Hong, M.T. Wu, F. Hsu, N. Z. Lien, S.Y. Wang, L.W. Yang, T. Yang, K.C. Chen, K. Hsieh, Rich Liu, Chih-Yuan Lu
{"title":"Scaling evaluation of BE-SONOS NAND flash beyond 20 nm","authors":"H. Lue, T. Hsu, S. Lai, Y. Hsiao, W.C. Peng, C.W. Liao, Y. Huang, S. Hong, M.T. Wu, F. Hsu, N. Z. Lien, S.Y. Wang, L.W. Yang, T. Yang, K.C. Chen, K. Hsieh, Rich Liu, Chih-Yuan Lu","doi":"10.1109/VLSIT.2008.4588584","DOIUrl":"https://doi.org/10.1109/VLSIT.2008.4588584","url":null,"abstract":"We have successfully fabricated and characterized sub-30 nm and sub-20 nm BE-SONOS NAND flash. Good device characteristics are achieved through two innovative processes: (1) a low-energy tilt-angle STI pocket implantation to suppress the STI corner edge effect, and (2) a drain offset using an additional oxide liner to improve the short-channel effect. The conventional self-boosting program-inhibit and ISPP (incremental step pulse programming) for MLC storage are demonstrated for 20 nm BE-SONOS NAND operation. Read current stability and read disturb life time are also evaluated. The estimated number of storage electrons is only 50-100, and for the first time we have demonstrated successful data retention after 150degC baking in the ldquofew-electronrdquo regime. Our results strongly suggest that BE-SONOS is a promising charge-trapping (CT) technology for NAND Flash scaling.","PeriodicalId":173781,"journal":{"name":"2008 Symposium on VLSI Technology","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122599536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Guillorn, Josephine B. Chang, Andres Bryant, Nicholas C. M. Fuller, Omer H. Dokumaci, X. Wang, J. Newbury, Katherina Babich, John A. Ott, B. Haran, Roy Yu, Christian Lavoie, D. Klaus, Ying Zhang, E. Sikorski, W. Graham, B. To, M. Lofaro, J. Tornello, Dinesh Koli, B. Yang, A. Pyzyna, D. Neumeyer, Marwan H. Khater, A. Yagishita, H. Kawasaki, Wilfried Haensch
{"title":"FinFET performance advantage at 22nm: An AC perspective","authors":"M. Guillorn, Josephine B. Chang, Andres Bryant, Nicholas C. M. Fuller, Omer H. Dokumaci, X. Wang, J. Newbury, Katherina Babich, John A. Ott, B. Haran, Roy Yu, Christian Lavoie, D. Klaus, Ying Zhang, E. Sikorski, W. Graham, B. To, M. Lofaro, J. Tornello, Dinesh Koli, B. Yang, A. Pyzyna, D. Neumeyer, Marwan H. Khater, A. Yagishita, H. Kawasaki, Wilfried Haensch","doi":"10.1109/VLSIT.2008.4588544","DOIUrl":"https://doi.org/10.1109/VLSIT.2008.4588544","url":null,"abstract":"At the 22 nm node, we estimate that superior electrostatics and reduced junction capacitance in FinFETs may provide a 13~23% reduction in delay relative to planar FETs. However, this benefit is offset by enhanced gate-to-source/drain capacitance (Cgs) in FinFETs. Here, we measure FinFET Cgs capacitance at 22 nm-like dimensions and determine that, with optimization, the FinFET capacitance penalty can be limited to <6%, resulting in an overall advantage of up to 17% over a planar technology.","PeriodicalId":173781,"journal":{"name":"2008 Symposium on VLSI Technology","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116697190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Ekbote, K. Benaissa, B. Obradovic, S. Liu, H. Shichijo, F. Hou, T. Blythe, T. Houston, S. Martin, Richard Taylor, A. Singh, H. Yang, G. Baldwin
{"title":"45nm low-power CMOS SoC technology with aggressive reduction of random variation for SRAM and analog transistors","authors":"S. Ekbote, K. Benaissa, B. Obradovic, S. Liu, H. Shichijo, F. Hou, T. Blythe, T. Houston, S. Martin, Richard Taylor, A. Singh, H. Yang, G. Baldwin","doi":"10.1109/VLSIT.2008.4588602","DOIUrl":"https://doi.org/10.1109/VLSIT.2008.4588602","url":null,"abstract":"Mobile system-on-chip (SoC) technologies require high-quality analog active and passive components along with low-power CMOS and dense SRAM. However, area scaling for both the SRAM bit cell and analog CMOS circuits is becoming increasingly difficult due to the impact of transistor random variation. To avoid added cost, co-optimizing the process for low random variation along with high performance and low power is required. We report a 45 nm lowpower technology with significantly reduced random variation for high yielding 0.255 mum2 SRAM arrays and analog transistors. Flexible RF and passive components for mobile SoCpsilas are also described. These process techniques enable continued 50% area scaling at 45 nm and beyond.","PeriodicalId":173781,"journal":{"name":"2008 Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129693259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Veloso, L. Witters, M. Demand, I. Ferain, N. Son, B. Kaczer, P. Roussel, E. Simoen, T. Kauerauf, C. Adelmann, S. Brus, O. Richard, H. Bender, T. Conard, R. Vos, R. Rooyackers, S. Van Elshocht, N. Collaert, K. De Meyer, S. Biesemans, M. Jurczak
{"title":"Flexible and robust capping-metal gate integration technology enabling multiple-VT CMOS in MuGFETs","authors":"A. Veloso, L. Witters, M. Demand, I. Ferain, N. Son, B. Kaczer, P. Roussel, E. Simoen, T. Kauerauf, C. Adelmann, S. Brus, O. Richard, H. Bender, T. Conard, R. Vos, R. Rooyackers, S. Van Elshocht, N. Collaert, K. De Meyer, S. Biesemans, M. Jurczak","doi":"10.1109/VLSIT.2008.4588545","DOIUrl":"https://doi.org/10.1109/VLSIT.2008.4588545","url":null,"abstract":"We report, for the first time, a comprehensive study on various capping integration options for WF engineering in MuGFET devices with TiN gate electrode: HfSiO/cap/TiN, cap/HfSiO/TiN and HfSiO/TiN/cap/TiN vs. reference deposition sequence HfSiO/TiN (cap = Al2O3 for pmos, and Dy2O3 or La2O3 for nmos). We show that: 1) low-VT values (Lt 0.3 V) are achieved for both nmos and pmos, with excellent process control and device behavior down to Lg ap 50 nm and WFIN ap 20 nm, for optimized gate stack configurations; 2) inserting a cap layer in-between TiN layers instead of HfSiO/cap/TiN leads to improved mobility, reduced CET without impacting JG, similar noise response and improved BTI behavior, with correction of the abnormal PBTI degradation seen for HfSiO/DyO/TiN. Is also enables simplified and more robust CMOS co-integration of low- and med-VT devices in the same wafer, avoiding loss in CET and damage of the host dielectric with the cap removal process.","PeriodicalId":173781,"journal":{"name":"2008 Symposium on VLSI Technology","volume":"214 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114005393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Mayuzumi, S. Yamakawa, D. Kosemura, M. Takei, J. Wang, T. Ando, Y. Tateshita, M. Tsukamoto, H. Wakabayashi, T. Ohno, A. Ogura, N. Nagashima
{"title":"Channel-stress study on gate-size effects for damascene-Gate pMOSFETs with top-cut compressive stress liner and eSiGe","authors":"S. Mayuzumi, S. Yamakawa, D. Kosemura, M. Takei, J. Wang, T. Ando, Y. Tateshita, M. Tsukamoto, H. Wakabayashi, T. Ohno, A. Ogura, N. Nagashima","doi":"10.1109/VLSIT.2008.4588588","DOIUrl":"https://doi.org/10.1109/VLSIT.2008.4588588","url":null,"abstract":"Damascene gate process enhances the drivability in shorter gate length region, as compared to conventional gate 1st process for pFETs with compressive stress SiN liner and embedded SiGe. The origin of the gate length effect is investigated for the first time by using the UV-Raman spectroscopy. Moreover, the relationship between channel strain and gate width for damascene gate pFETs is analyzed and the effect is also demonstrated. It is found that channel strain is considerably enhanced in shorter gate length and narrower gate width by the combination of damascene gate process and stress enhancement techniques.","PeriodicalId":173781,"journal":{"name":"2008 Symposium on VLSI Technology","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129830925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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