Proceedings of Japan International Electronic Manufacturing Technology Symposium最新文献

{"title":"Low Frequency Noise Measurements On The Light Output And Current Of Laser Diodes","authors":"Shiyuan Yang, T. Mizunami","doi":"10.1109/IEMT.1993.639765","DOIUrl":"https://doi.org/10.1109/IEMT.1993.639765","url":null,"abstract":"Summary A low frequency noise analysing system is set up with a multi-channel detector. The multi-channel detector includes a PCD Image Sensor which has 256 sensing elements. Light output of a laser diode is divided into various wavelengths. The light spectral intensities are measured at various wavelengths.","PeriodicalId":170695,"journal":{"name":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128903062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Molding Compound Trends In A Denser Packaging World. I. Technology Evolution","authors":"L. Nguyen, R. Lo, J.G. Belimi","doi":"10.1109/IEMT.1993.639753","DOIUrl":"https://doi.org/10.1109/IEMT.1993.639753","url":null,"abstract":"","PeriodicalId":170695,"journal":{"name":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126897858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low Temperature Co-fireable Multilayer Ceramic Substrate With Internal Capacitor","authors":"H. Ochi, Y. Baba, S. Segawa, S. Fukunaga","doi":"10.1109/IEMT.1993.639353","DOIUrl":"https://doi.org/10.1109/IEMT.1993.639353","url":null,"abstract":"This paper discusses the newly developed I ow temperature co-fi reable mu1 t i layer ceramic substrate with internal capacitor on structure, materials , fabrication process and properties of internal capacitor.","PeriodicalId":170695,"journal":{"name":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127119282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Automatically Assembled Miniaturized SMD Isolator For 1.9ghz Band Communications Systems","authors":"Y. Ishikawa, T. Okada, Hiroki Dejima, Takahiro Joudo, Takashi Kawanami","doi":"10.1109/IEMT.1993.639376","DOIUrl":"https://doi.org/10.1109/IEMT.1993.639376","url":null,"abstract":"A miniaturized SMD isolator has been developed for 1.9GHz band communication systems. The dimensions of the isolator are '7x7x3mm (0.15cc) and the weight is 0.50g. By reducing the number of elements and simplifying the structure stacking, assembly has been automated. And a height of 3mm is made possible by stacking some of the elements. The terminals for the surface mount specification are composed of six pieces. Fixed strength of terminals with PCB (printed circuit board) has improved about 40% in comparison with a conventional model being formed four terminals. It is pos:;ible to design the isolator for 1.3GHz by adjusting the capacitance. Selected the capacitors by automatic capacitor sorting machine (ACSM) in a high speed, the assembly time has been cut by about 15%. 1. INTRODUCT~ON three layers of PCB. Two kinds are used, one is for an isolator, and the other for a circulator. The center conductors of each layer have been insulated and oriented at 120\" degrees to each other, One end of each conductor is connected to a ground substrate via the through hole and the other end is connected to a capacitor. 100-ohm chip resistors are connected in parallel to divide the power dissipation in order to enable a power rating. For a circulator, they are not used. A resin case with molded copper U0 terminals and ground terminals is used. One end of each terminal is formed in SMD type, the other end is connected with the main substrate. A magnet applies a dc magnetic field to the femte and is located in a hole in the top of the resin case. Simple, stacked element design allows automated assembly. With dense packing, dimensions are reduced to 7x7x3mm(max) and a weight of 0.5g. With the iricrease in mobile communications systems, such as portable telephones, there has been a consequent reduction in size, weight. and cost of these systems. A low cost, low profile isolator suitable for SMD has been developed to satisfy these requiremcnts. A technique for producing a small SMD isolator for 300MHz and 800MHz bands has already been reported'11[21, but none has been produced for the 1.9GHz band. We have automated one of the assembly processes. To cut down the cost of elements and the assembly time, the structure incorporates common elements and processes. With this structure, which makes possible the automation of all the assembly processes, assembly time and cost are halved. This paper describes the construction, design, manufacturing process and performance of the isolator.","PeriodicalId":170695,"journal":{"name":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131420282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Survey Of Critical Metrology Needs For IC Interconnect Processes Based On Assessment By Quality Function Deployment (qfd) Methodology","authors":"D. E. Pope, S. Prough, K. Wieneke","doi":"10.1109/IEMT.1993.639739","DOIUrl":"https://doi.org/10.1109/IEMT.1993.639739","url":null,"abstract":"Parallel surveys of users and suppliers were employed to evaluate matching of needs VS. product planning €or development of metrology tools and equipment to control IC chip to package interconnect processes. The surveys also compared actual supplier plans vs. a \"rational behavior\" model represented by a QFD customer requirement planning matrix. While general agreement is evident about needs to change from ouput measurements to in-line process control and pre-process problem prevention, both users and suppliers seem to be continuing use of outdated wire pull and visual inspection methods. This stalemate may be due to ineffective deployment of \"voice of the customer\" requirments into specific product plans and industry standards. QFD methods seem especially suitable for application to clarify emerging trends and to facilitate industry acceptance of appropriate new measurement technologies.","PeriodicalId":170695,"journal":{"name":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128224278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Intelligent Adaptive Manufacturing Method With App~cation To Electronics Assembly","authors":"C. R. Standridga","doi":"10.1109/IEMT.1993.639741","DOIUrl":"https://doi.org/10.1109/IEMT.1993.639741","url":null,"abstract":"r Demand for higher product quality and the increasing complexity of manufacturing processes give rise to the need for new manufacturing methods. We describe a new intelligent, adaptive manufacturing method intended to meet these needs. The new method uses on-line intelligent processing for assessment, diagnosis, and adjustment; integrates information and hardware throughout the manufacturing process; and employs computer models to assess manufacturing operations. Application of the new method to electronics assembly is discussed.","PeriodicalId":170695,"journal":{"name":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115898706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Planarization Process Of Copper-polyimide Thin Film Multilayer Substrate","authors":"Yukio Kasuya, Y. Takahashi, Yutaka Uno, Y. Iguchi, T. Kanamori","doi":"10.1109/IEMT.1993.639284","DOIUrl":"https://doi.org/10.1109/IEMT.1993.639284","url":null,"abstract":"","PeriodicalId":170695,"journal":{"name":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117165349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A New Washingless Hybrid-mounting Technique For Bare Chip ICs And SMDs","authors":"H. Ozaki","doi":"10.1109/IEMT.1993.639288","DOIUrl":"https://doi.org/10.1109/IEMT.1993.639288","url":null,"abstract":"With the development of SMT(Surface Mount Technology), the semiconductor mounting technique is becoming more important than ever. We have debeloped a new hybrid-mounting technique for bare chip ICs and SMDs, which does not require a washing process. Until now washing process was essential for hybrid mounting because the bare chip ICs were mounted after reflow soldering of the SMDs. We have succeeded in eliminating the washing process by changing the order of mounting the SMDs and ICs ,and by developing a new metal screen mask.","PeriodicalId":170695,"journal":{"name":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114800786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design Abstract For Manufacturing Of High Density Wire Bonded VLSI Packages","authors":"J.-Y. Guernalec, J. Joly, X. Saint-martin","doi":"10.1109/IEMT.1993.639805","DOIUrl":"https://doi.org/10.1109/IEMT.1993.639805","url":null,"abstract":"The increasing size of VLSI silicon chips, the larger and larger number of I/O’s, a need for higher electrical performances increase the ceramic package complexity and, therefore, the package and assembly costs. One of the most important parameter in packaging cost analysis is the assembly yield which can drastically affect the cost of assembled components. Based on our experience in the assembly of thousands of 316 I/Os VLSIs in ceramic single chip packages, we shall analyse how to optimize the design of ceramic packages and silicon chips in order to increase their assembly yield. We shall describe successively the design rules for package (materials. metallizations, cavity, lid sealing, lead attach) used for optimizing die bonding, wire bonding, hermiticity and lead attach yields. Recommendations will be given for silicon chips design. Using these rules, wire bonding yield as high as 99.998 % per wire and assembly yields a5 high as 98 % per package are actualy obtained on manufacturing runs. A procedure taking into account the wire bonding machine accuracy and the ceramic packages characteristics permits to predetermine the wire bonding yield, one of the major factors affecting the assembly yield. Therefore, it is possible to predict the assembly cost of packages at their design stage. Recent developments in terms of high density wire bonding on silicon chips and metalized ceramics allow us to forecast high assembly yields on future VLSI packages when using very large silicon chips.","PeriodicalId":170695,"journal":{"name":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128325589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Robust Fault Detection In Technological Equipment","authors":"A. Zhirabok, O. Preobrazhenskaya","doi":"10.1109/IEMT.1993.639743","DOIUrl":"https://doi.org/10.1109/IEMT.1993.639743","url":null,"abstract":"","PeriodicalId":170695,"journal":{"name":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131066041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}