Design Abstract For Manufacturing Of High Density Wire Bonded VLSI Packages

Abstract

The increasing size of VLSI silicon chips, the larger and larger number of I/O’s, a need for higher electrical performances increase the ceramic package complexity and, therefore, the package and assembly costs. One of the most important parameter in packaging cost analysis is the assembly yield which can drastically affect the cost of assembled components. Based on our experience in the assembly of thousands of 316 I/Os VLSIs in ceramic single chip packages, we shall analyse how to optimize the design of ceramic packages and silicon chips in order to increase their assembly yield. We shall describe successively the design rules for package (materials. metallizations, cavity, lid sealing, lead attach) used for optimizing die bonding, wire bonding, hermiticity and lead attach yields. Recommendations will be given for silicon chips design. Using these rules, wire bonding yield as high as 99.998 % per wire and assembly yields a5 high as 98 % per package are actualy obtained on manufacturing runs. A procedure taking into account the wire bonding machine accuracy and the ceramic packages characteristics permits to predetermine the wire bonding yield, one of the major factors affecting the assembly yield. Therefore, it is possible to predict the assembly cost of packages at their design stage. Recent developments in terms of high density wire bonding on silicon chips and metalized ceramics allow us to forecast high assembly yields on future VLSI packages when using very large silicon chips.