2011 IEEE 6th International Design and Test Workshop (IDT)最新文献_第2页

4-D parity codes for soft error correction in aerospace applications 航空航天应用中软纠错用四维奇偶校验码

2011 IEEE 6th International Design and Test Workshop (IDT) Pub Date : 2011-12-01 DOI: 10.1109/IDT.2011.6123111

Muhammad Imran, Z. Al-Ars, G. Gaydadjiev

引用次数: 2

Design of tunable continuous-time quadrature bandpass delta-sigma modulators 可调谐连续时间正交带通δ - σ调制器的设计

2011 IEEE 6th International Design and Test Workshop (IDT) Pub Date : 2011-12-01 DOI: 10.1109/IDT.2011.6123110

Khaled Sakr, M. Dessouky, A. Zekry

引用次数: 1

On modeling and optimizing cost in 3D Stacked-ICs 三维堆叠集成电路的建模与成本优化

2011 IEEE 6th International Design and Test Workshop (IDT) Pub Date : 2011-12-01 DOI: 10.1109/IDT.2011.6123096

M. Taouil, S. Hamdioui, E. Marinissen

{"title":"On modeling and optimizing cost in 3D Stacked-ICs","authors":"M. Taouil, S. Hamdioui, E. Marinissen","doi":"10.1109/IDT.2011.6123096","DOIUrl":"https://doi.org/10.1109/IDT.2011.6123096","url":null,"abstract":"3D-Stacked IC (3D-SIC) technology is one of the emerging technologies with many benefits such as higher performance and heterogeneous integration. During the manufacturing of such ICs, tests can be applied at different moments such as (a) before the stacking process, (b) after the creation of each partial stacked IC, (c) after the creation of the complete stack, and (d) after packaging of the stack. Moreover, each applied test may target interconnects, one or more dies, or even both. This results into a huge number of test flows, each with its own specific test cost. Choosing an efficient and appropriate test flow providing the required outgoing product quality (for a given design and manufacturing parameters) is extremely important in order to make 3D-SIC business profitable. This paper discusses a tool for 3D-SIC test cost modeling; It gives the requirements and classifies them in design, manufacturing, test, packaging and logistics. It further covers user-cases and shows how the tool can be used at an early design stage in order to select the most efficient test flow for given input parameters (related either to manufacturing, test, packaging or logistics); hence, optimize the design and/or include the required DFT to support the selected test flow. The tool can be also used for sensitivity analysis where the impact of parameter changes on the test cost can be analyzed.","PeriodicalId":167786,"journal":{"name":"2011 IEEE 6th International Design and Test Workshop (IDT)","volume":"82 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114093851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Process-variation and temperature aware soc test scheduling using particle swarm optimization 基于粒子群优化的工艺变化和温度敏感soc测试调度

2011 IEEE 6th International Design and Test Workshop (IDT) Pub Date : 2011-12-01 DOI: 10.1109/IDT.2011.6123092

Nima Aghaee, Zebo Peng, P. Eles

引用次数: 6

ReverseAge: An online NBTI combating technique using time borrowing ReverseAge:一种利用时间借用的在线NBTI对抗技术

2011 IEEE 6th International Design and Test Workshop (IDT) Pub Date : 2011-12-01 DOI: 10.1109/IDT.2011.6123098

Seyab Khan, S. Hamdioui

引用次数: 3

Adjustable supply voltages and refresh cycle for process variations, temperature changes, and device degradation adaptation in 1T1C embedded DRAM 可调电源电压和刷新周期的工艺变化，温度变化，并在1T1C嵌入式DRAM器件退化适应

2011 IEEE 6th International Design and Test Workshop (IDT) Pub Date : 2011-12-01 DOI: 10.1109/IDT.2011.6123115

L. Tran, F. Kurdahi, A. Eltawil, A. Aljumah

引用次数: 1

Performance and functional test of flip-flops using ring oscillator structure 环形振荡器结构触发器的性能和功能测试

2011 IEEE 6th International Design and Test Workshop (IDT) Pub Date : 2011-12-01 DOI: 10.1109/IDT.2011.6123099

R. Ribas, A. Reis, A. Ivanov

引用次数: 3

Yield enhancement flow for analog and full custom designs reliability-rules automatic application 产量增强流模拟和完全定制设计可靠性规则自动应用

2011 IEEE 6th International Design and Test Workshop (IDT) Pub Date : 2011-12-01 DOI: 10.1109/IDT.2011.6123105

A. Abdulghany, R. Salem, L. Capodieci, S. Malik

引用次数: 4

The effectiveness of delay and IDDT tests in detecting resistive open defects for nanometer CMOS adder circuits 延迟和IDDT测试在检测纳米CMOS加法器电阻性开路缺陷中的有效性

2011 IEEE 6th International Design and Test Workshop (IDT) Pub Date : 2011-12-01 DOI: 10.1109/IDT.2011.6123101

L. Hamieh, N. Mehdi, Ghazalah Omeirat, A. Chehab, A. Kayssi

{"title":"The effectiveness of delay and IDDT tests in detecting resistive open defects for nanometer CMOS adder circuits","authors":"L. Hamieh, N. Mehdi, Ghazalah Omeirat, A. Chehab, A. Kayssi","doi":"10.1109/IDT.2011.6123101","DOIUrl":"https://doi.org/10.1109/IDT.2011.6123101","url":null,"abstract":"In this paper we evaluate the effectiveness of different testing schemes in detecting resistive-open defects in adder circuits implemented using different CMOS technologies (45 nm, 32 nm, 22 nm and 16 nm). We assess the detection capabilities of four testing techniques taking into consideration the wide process variations associated with the different nanometer technologies. The first three techniques are based on the transient supply current, iDDT, and the fourth technique is based on delay testing. The first iDDT method uses the RMS value of the wavelet transform of the transient power supply or ground currents. The second one uses the normalized RMS value of the wavelet transform. The third one uses the peak value of iDDT. The fourth technique measures the primary input-to-output delay. The experimental results show that the delay test is the most effective among all tests. The iDDT test with normalized RMS value of wavelet transform comes second. The other two tests were less effective than the first two, especially in the case of smaller technologies (22 and 16 nm).","PeriodicalId":167786,"journal":{"name":"2011 IEEE 6th International Design and Test Workshop (IDT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130079432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Bipolar OxRRAM memory array reliability evaluation based on fault injection 基于故障注入的双极OxRRAM存储阵列可靠性评估

2011 IEEE 6th International Design and Test Workshop (IDT) Pub Date : 2011-12-01 DOI: 10.1109/IDT.2011.6123106

H. Aziza, M. Bocquet, J. Portal, C. Muller

引用次数: 20