A. H. Gholamipour, Kyprianos Papademetriou, F. Kurdahi, A. Dollas, A. Eltawil
{"title":"Area, reconfiguration delay and reliability trade-offs in designing reliable multi-mode FIR filters","authors":"A. H. Gholamipour, Kyprianos Papademetriou, F. Kurdahi, A. Dollas, A. Eltawil","doi":"10.1109/IDT.2011.6123107","DOIUrl":"https://doi.org/10.1109/IDT.2011.6123107","url":null,"abstract":"Wide range of digital systems from wireless devices to multi-media terminals are characterized by their multi-mode behavior. Many of these systems are deployed in high-radiation environments [5]. SRAM-based FPGAs are popular platforms to implement multi-mode systems, because of their high performance and reconfigurability. However, high susceptibility of FPGAs toward Soft Errors makes them less-than-reliable platforms. To overcome the reliability issue, various redundancy techniques have been proposed. These techniques exhibit different design and reliability characteristics. Considering the combined effect of design decisions and reliability techniques on system characteristics a coherent strategy should be devised to meet system requirements and constraints. In this work we propose a method to explore the design space for implementing a reliable multi-mode system. As we will show, different selections of design parameters and redundancy techniques generate a range of solutions which trade-off total area, reconfiguration overhead and reliability of the system. The choice of a specific solution remains a decision made by the system-designer.","PeriodicalId":167786,"journal":{"name":"2011 IEEE 6th International Design and Test Workshop (IDT)","volume":"298 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132627379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Layout-aware high performance interconnects for Network-on-Chip design in deep nanometer technologies","authors":"G. Reehal, M. Ismail","doi":"10.1109/IDT.2011.6123102","DOIUrl":"https://doi.org/10.1109/IDT.2011.6123102","url":null,"abstract":"As IC geometries continue to shrink into the deep nanometer regime, interconnects can have a large impact on overall system performance, power consumption, cost and reliability. In 90 nm or lower technologies, wiring capacitance dominates gate capacitance, thus rapidly leading to increased interconnect-induced delay. Moreover, coupling capacitance becomes significant between adjacent wires due to tighter geometries and can no longer be ignored as a second order effect. As a consequence, traditional top-down approach taken in design methodology for a NoC based complex SoC designs is no longer effective. This paper address the impact of nanometer layout on the design of NoC, and shows the necessity to consider interconnect parasitic effects in early stages of design even when no physical layout is available. Global interconnects with and without repeater insertion are considered. The effects of the width and spacing of global interconnects on NoC performance such as delay, bandwidth, total repeater area and power dissipation is analyzed.","PeriodicalId":167786,"journal":{"name":"2011 IEEE 6th International Design and Test Workshop (IDT)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124542019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Novel Adaptive Virtual Channels technique for NoC switch","authors":"Rabab Ezz-Eldin, M. El-Moursy, A. M. Refaat","doi":"10.1109/IDT.2011.6123093","DOIUrl":"https://doi.org/10.1109/IDT.2011.6123093","url":null,"abstract":"Adaptive Virtual Channel (AVC) is proposed as an efficient novel technique to reduce power dissipation of NoC switch. The proposed NoC switch employs power supply gating to reduce the power dissipation without degrading network performance. Hierarchical multiplexing tree is used to achieve efficient AVC. AVC uses hierarchical multiplexing tree and power gating mechanism to reduce both dynamic and leakage power dissipation of the switch. AVC technique is proposed to reduce the active area using hierarchical multiplexing tree. The dynamic power reduces by 60%. Using the leakage power reduction technique, the average leakage power consumption of Adaptive Virtual Channels is reduced by up to 97%.","PeriodicalId":167786,"journal":{"name":"2011 IEEE 6th International Design and Test Workshop (IDT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130703471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Survey of fault tolerance techniques for shared memory multicore/multiprocessor systems","authors":"Hamid Mushtaq, Z. Al-Ars, K. Bertels","doi":"10.1109/IDT.2011.6123094","DOIUrl":"https://doi.org/10.1109/IDT.2011.6123094","url":null,"abstract":"With the advent of modern nano-scale technology, it has become possible to implement multiple processing cores on a single die. The shrinking transistor sizes however have made reliability a concern for such systems as smaller transistors are more prone to permanent as well as transient faults. To reduce the probability of failures of such systems, online fault tolerance techniques can be applied. These techniques need to be efficient as they execute concurrently with applications running on such systems. This paper discusses the challenges involved in online fault tolerance and existing work which tackles these challenges. We classify fault tolerance into four different steps which are proactive fault management, error detection, fault diagnosis and recovery and discuss related work for each step, with focus on techniques for shared memory multicore/multiprocessor systems. We also highlight the additional difficulties in tolerating faults for parallel execution on shared memory multicore/multiprocessor systems.","PeriodicalId":167786,"journal":{"name":"2011 IEEE 6th International Design and Test Workshop (IDT)","volume":"448 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125782948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}