2011 IEEE 6th International Design and Test Workshop (IDT)最新文献

Analog performance prediction based on archimedean copulas generation algorithm 基于阿基米德copula生成算法的模拟性能预测

2011 IEEE 6th International Design and Test Workshop (IDT) Pub Date : 2011-12-01 DOI: 10.1109/IDT.2011.6123095

Kamel Beznia, A. Bounceur, R. Euler

{"title":"Analog performance prediction based on archimedean copulas generation algorithm","authors":"Kamel Beznia, A. Bounceur, R. Euler","doi":"10.1109/IDT.2011.6123095","DOIUrl":"https://doi.org/10.1109/IDT.2011.6123095","url":null,"abstract":"Testing analog circuits is a complex and very time consuming task. In contrary to digital circuits, testing analog circuits needs different configurations, each of them targets a certain set of output parameters which are the performances and the test measures. One of the solutions to simplify the test task and optimize test time is the reduction of the number of to-be-tested performances by eliminating redundant ones. However, the main problem with such a solution is the identification of redundant performances. Traditional methods based on calculation of the correlation between different performances or on the defect level are shown to be not sufficient. This paper presents a new method based on the Archimedean copula generation algorithm. It predicts the performance value from each output parameter value based on the dependence (copula) between the two values. Therefore, different performances can be represented by a single output parameter; as a result, less test configurations are required. To validate the proposed approach, a CMOS imager with two performances and one test measure is used. The simulation results show that the two performances can be replaced by a single test measure. Industrial results are also reported to prove the superiority of the proposed approach.1","PeriodicalId":167786,"journal":{"name":"2011 IEEE 6th International Design and Test Workshop (IDT)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133229603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

An electrical-aware parametric DFM solution for analog circuits 模拟电路的电感知参数DFM解决方案

2011 IEEE 6th International Design and Test Workshop (IDT) Pub Date : 2011-12-01 DOI: 10.1109/IDT.2011.6123104

R. Salem, A. Arafa, Sherif Hany, Abdelrahman ElMously, H. Eissa, M. Dessouky, D. Nairn, M. Anis

{"title":"An electrical-aware parametric DFM solution for analog circuits","authors":"R. Salem, A. Arafa, Sherif Hany, Abdelrahman ElMously, H. Eissa, M. Dessouky, D. Nairn, M. Anis","doi":"10.1109/IDT.2011.6123104","DOIUrl":"https://doi.org/10.1109/IDT.2011.6123104","url":null,"abstract":"Today, many of the approaches that are commonly referred to as physical DFM techniques only address catastrophic defects and systematic process variations. These techniques include spreading wires, doubling vias, identification of critical areas in the circuit that are especially susceptible to defects, and identification of proximity effects caused by the lithography process. However, physical DFM tools are purely “geometric”, in that they work to preserve shape fidelity without any knowledge of the impact on the electrical characteristics of the shapes that are manufactured in silicon. While these techniques have proven useful in reducing functional failures and increasing overall yield by a few percentage points, they completely ignore the more important category of parametric failures. The proposed solution presented in this chapter specifically helps to address the parametric performance modeling problems encountered at smaller geometries. As this solution drives design requirements into physical layout design and moves layout awareness upstream into design, useful information about the design (on the physical and electrical level) is captured, analyzed, and simulated. Deviations in the electrical characteristics due to physical layout and process variations, are identified and highlighted on the design. These deviations are referred as electrical hotspots (e-hotspots). To validate this work, The proposed e-hotspot detection engine is verified against silicon wafer data for a level shifter circuit designed at 130nm. The e-hotspot devices with high variation in DC current and causing parametric failure, are identified.","PeriodicalId":167786,"journal":{"name":"2011 IEEE 6th International Design and Test Workshop (IDT)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133056463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Python-based layout-aware analog design methodology for nanometric technologies 基于python的纳米技术布局感知模拟设计方法

2011 IEEE 6th International Design and Test Workshop (IDT) Pub Date : 2011-12-01 DOI: 10.1109/IDT.2011.6123103

Stephanie Youssef, F. Javid, D. Dupuis, R. Iskander, M. Louërat

引用次数: 23

Fault detection and diagnoses methodology for adaptive digitally-calibrated pipelined ADCs 自适应数字校准流水线adc的故障检测与诊断方法

2011 IEEE 6th International Design and Test Workshop (IDT) Pub Date : 2011-12-01 DOI: 10.1109/IDT.2011.6123097

M. Abbas

{"title":"Fault detection and diagnoses methodology for adaptive digitally-calibrated pipelined ADCs","authors":"M. Abbas","doi":"10.1109/IDT.2011.6123097","DOIUrl":"https://doi.org/10.1109/IDT.2011.6123097","url":null,"abstract":"This paper presents a cost-effective methodology for fault detection and diagnosis in the adaptive digitally-calibrated pipelined ADCs. In the proposed method, the analog portions of the design are tested utilizing the digital output codes. The test stimulus is generated on-chip. In contrast with the conventional method where the test is usually done at the end of the calibration process, the proposed method utilizes the uncalibrated output codes of the DUT to generate the code error signature (Cεs), which is the difference between the expected (ideal) and the uncalibrated output codes. Interpreting (Cεs), the process of fault isolation and fault value assessment can be done. To demonstrate the methodology, a ten-stage digitally-calibrated pipelined ADC is modeled and simulated using MATLAB. Faults having different type and values are intentionally injected in different places of the design. The simulation results show that Cεs of each fault has pattern dependence on the faulty portion, fault type and fault value. Therefore, the faulty (or even the weak) portion(s) of the DUT can be identified, which is useful for enhancing the reliability of the subsequent design generation.","PeriodicalId":167786,"journal":{"name":"2011 IEEE 6th International Design and Test Workshop (IDT)","volume":"928 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120942103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Validation & Verification of an EDA automated synthesis tool EDA自动合成工具的验证和验证

2011 IEEE 6th International Design and Test Workshop (IDT) Pub Date : 2011-12-01 DOI: 10.1109/IDT.2011.6123100

S. Carlo, Giulio Gambardella, Marco Indaco, Daniele Rolfo, P. Prinetto

引用次数: 1

Body contact based TSV equalizer 基于身体接触的TSV均衡器

2011 IEEE 6th International Design and Test Workshop (IDT) Pub Date : 2011-12-01 DOI: 10.1109/IDT.2011.6123113

K. Mohamed, A. El-Rouby, Y. Ismail, H. Ragai

引用次数: 1

Digital circuits verification with consideration of destabilizing factors 考虑不稳定因素的数字电路验证

2011 IEEE 6th International Design and Test Workshop (IDT) Pub Date : 2011-12-01 DOI: 10.1109/IDT.2011.6123109

R. Goldman, Vazgen Melikyan, E. Babayan

引用次数: 1

On modeling and optimizing cost in 3D Stacked-ICs 三维堆叠集成电路的建模与成本优化

2011 IEEE 6th International Design and Test Workshop (IDT) Pub Date : 2011-12-01 DOI: 10.1109/IDT.2011.6123096

M. Taouil, S. Hamdioui, E. Marinissen

{"title":"On modeling and optimizing cost in 3D Stacked-ICs","authors":"M. Taouil, S. Hamdioui, E. Marinissen","doi":"10.1109/IDT.2011.6123096","DOIUrl":"https://doi.org/10.1109/IDT.2011.6123096","url":null,"abstract":"3D-Stacked IC (3D-SIC) technology is one of the emerging technologies with many benefits such as higher performance and heterogeneous integration. During the manufacturing of such ICs, tests can be applied at different moments such as (a) before the stacking process, (b) after the creation of each partial stacked IC, (c) after the creation of the complete stack, and (d) after packaging of the stack. Moreover, each applied test may target interconnects, one or more dies, or even both. This results into a huge number of test flows, each with its own specific test cost. Choosing an efficient and appropriate test flow providing the required outgoing product quality (for a given design and manufacturing parameters) is extremely important in order to make 3D-SIC business profitable. This paper discusses a tool for 3D-SIC test cost modeling; It gives the requirements and classifies them in design, manufacturing, test, packaging and logistics. It further covers user-cases and shows how the tool can be used at an early design stage in order to select the most efficient test flow for given input parameters (related either to manufacturing, test, packaging or logistics); hence, optimize the design and/or include the required DFT to support the selected test flow. The tool can be also used for sensitivity analysis where the impact of parameter changes on the test cost can be analyzed.","PeriodicalId":167786,"journal":{"name":"2011 IEEE 6th International Design and Test Workshop (IDT)","volume":"82 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114093851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Process-variation and temperature aware soc test scheduling using particle swarm optimization 基于粒子群优化的工艺变化和温度敏感soc测试调度

2011 IEEE 6th International Design and Test Workshop (IDT) Pub Date : 2011-12-01 DOI: 10.1109/IDT.2011.6123092

Nima Aghaee, Zebo Peng, P. Eles

引用次数: 6

ReverseAge: An online NBTI combating technique using time borrowing ReverseAge:一种利用时间借用的在线NBTI对抗技术

2011 IEEE 6th International Design and Test Workshop (IDT) Pub Date : 2011-12-01 DOI: 10.1109/IDT.2011.6123098

Seyab Khan, S. Hamdioui

引用次数: 3