An electrical-aware parametric DFM solution for analog circuits

Abstract

Today, many of the approaches that are commonly referred to as physical DFM techniques only address catastrophic defects and systematic process variations. These techniques include spreading wires, doubling vias, identification of critical areas in the circuit that are especially susceptible to defects, and identification of proximity effects caused by the lithography process. However, physical DFM tools are purely “geometric”, in that they work to preserve shape fidelity without any knowledge of the impact on the electrical characteristics of the shapes that are manufactured in silicon. While these techniques have proven useful in reducing functional failures and increasing overall yield by a few percentage points, they completely ignore the more important category of parametric failures. The proposed solution presented in this chapter specifically helps to address the parametric performance modeling problems encountered at smaller geometries. As this solution drives design requirements into physical layout design and moves layout awareness upstream into design, useful information about the design (on the physical and electrical level) is captured, analyzed, and simulated. Deviations in the electrical characteristics due to physical layout and process variations, are identified and highlighted on the design. These deviations are referred as electrical hotspots (e-hotspots). To validate this work, The proposed e-hotspot detection engine is verified against silicon wafer data for a level shifter circuit designed at 130nm. The e-hotspot devices with high variation in DC current and causing parametric failure, are identified.