产量增强流模拟和完全定制设计可靠性规则自动应用

A. Abdulghany, R. Salem, L. Capodieci, S. Malik
{"title":"产量增强流模拟和完全定制设计可靠性规则自动应用","authors":"A. Abdulghany, R. Salem, L. Capodieci, S. Malik","doi":"10.1109/IDT.2011.6123105","DOIUrl":null,"url":null,"abstract":"As the variations of shrunk processes increase at rapid rate, the performance of fabricated analog and full custom chips remarkably fluctuate. This paper describes an effective automatic flow for reliability rules automatic application onto analog and full-custom ASIC designs, without introducing any new design rules check (DRC) violations in input design. This Yield enhancement flow has shown good improvements on used test designs, and ran in reasonable time. Based on the standardization methodology used, additional foundry Yield-enhancement-related recommendations can be also developed as extension to this flow seamlessly providing easy and quick new technology adoption and short Turnaround Time (TAT).","PeriodicalId":167786,"journal":{"name":"2011 IEEE 6th International Design and Test Workshop (IDT)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Yield enhancement flow for analog and full custom designs reliability-rules automatic application\",\"authors\":\"A. Abdulghany, R. Salem, L. Capodieci, S. Malik\",\"doi\":\"10.1109/IDT.2011.6123105\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"As the variations of shrunk processes increase at rapid rate, the performance of fabricated analog and full custom chips remarkably fluctuate. This paper describes an effective automatic flow for reliability rules automatic application onto analog and full-custom ASIC designs, without introducing any new design rules check (DRC) violations in input design. This Yield enhancement flow has shown good improvements on used test designs, and ran in reasonable time. Based on the standardization methodology used, additional foundry Yield-enhancement-related recommendations can be also developed as extension to this flow seamlessly providing easy and quick new technology adoption and short Turnaround Time (TAT).\",\"PeriodicalId\":167786,\"journal\":{\"name\":\"2011 IEEE 6th International Design and Test Workshop (IDT)\",\"volume\":\"43 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE 6th International Design and Test Workshop (IDT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IDT.2011.6123105\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE 6th International Design and Test Workshop (IDT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IDT.2011.6123105","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

摘要

随着缩制工艺变化的快速增加,制造模拟芯片和全定制芯片的性能波动很大。本文描述了一种有效的自动流程,将可靠性规则自动应用于模拟和全定制ASIC设计,而不引入任何新的输入设计规则检查(DRC)违规。该良率增强流程对现有试验设计有较好的改进,且运行时间合理。基于所使用的标准化方法,还可以开发其他与铸造成品率提高相关的建议,作为该流程的无缝扩展,提供简单快速的新技术采用和短周转时间(TAT)。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Yield enhancement flow for analog and full custom designs reliability-rules automatic application
As the variations of shrunk processes increase at rapid rate, the performance of fabricated analog and full custom chips remarkably fluctuate. This paper describes an effective automatic flow for reliability rules automatic application onto analog and full-custom ASIC designs, without introducing any new design rules check (DRC) violations in input design. This Yield enhancement flow has shown good improvements on used test designs, and ran in reasonable time. Based on the standardization methodology used, additional foundry Yield-enhancement-related recommendations can be also developed as extension to this flow seamlessly providing easy and quick new technology adoption and short Turnaround Time (TAT).
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信