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[1992] Proceedings 29th ACM/IEEE Design Automation Conference最新文献

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Equivalence of robust delay-fault and single stuck-fault test generation 鲁棒延迟故障与单卡故障测试生成的等价性
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227841
A. Saldanha, R. Brayton, A. Sangiovanni-Vincentelli
{"title":"Equivalence of robust delay-fault and single stuck-fault test generation","authors":"A. Saldanha, R. Brayton, A. Sangiovanni-Vincentelli","doi":"10.1109/DAC.1992.227841","DOIUrl":"https://doi.org/10.1109/DAC.1992.227841","url":null,"abstract":"A link between the problems of robust delay-fault and single stuck-fault test generation is established. In particular, it is proved that all the robust test vector pairs for any path delay-fault in a network are directly obtained by all the test vectors for a corresponding single stuck-fault in a modified network. Since single stuck-fault test generation is a well solved problem, this result yields an efficient algorithm for robust delay-fault test generation. Experimental results demonstrate the efficiency of the proposed technique.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115789798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 55
Symbolic prime generation for multiple-valued functions 多值函数的符号素数生成
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227865
Bill Lin, O. Coudert, J. Madre
{"title":"Symbolic prime generation for multiple-valued functions","authors":"Bill Lin, O. Coudert, J. Madre","doi":"10.1109/DAC.1992.227865","DOIUrl":"https://doi.org/10.1109/DAC.1992.227865","url":null,"abstract":"The authors present new techniques based on the implicit representation and generation of primes for multiple-valued functions with sets of primes several orders of magnitude larger than existing methods. The key idea that makes this computation possible is the symbolic representation of multiple-valued cubes in a characteristic function form called the characteristic-cube function. This symbolic representation can be efficiently denoted using a binary decision diagram (BDD), which is known to be a very compact representation for Boolean formulas. Since there is no direct correspondence between the number of elements in a characteristic function and the size of the BDD representation that denotes it, very large sets of primes may be captured symbolically using the characteristic-cube function representation. Functions with other 10/sup 10/ primes have been successfully generated by using the proposed method.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130949895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Certified timing verification and the transition delay of a logic circuit 逻辑电路的认证时间验证和转换延迟
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227744
S. Devadas, K. Keutzer, S. Malik, Albert R. Wang
{"title":"Certified timing verification and the transition delay of a logic circuit","authors":"S. Devadas, K. Keutzer, S. Malik, Albert R. Wang","doi":"10.1109/DAC.1992.227744","DOIUrl":"https://doi.org/10.1109/DAC.1992.227744","url":null,"abstract":"The transition delay of a circuit is examined. It is shown that the transition delay of a circuit can differ from the floating delay even in the presence of arbitrary monotonic speedups in the circuit. This result is used to derive a procedure which directly computes the transition delay of a circuit. Experimental results of applying the transition delay computation procedure to a number of benchmark examples are given. The most practical benefit of this procedure is that it not only results in a delay calculation but also produces a vector sequence that may be timing simulated to certify static timing verification.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131765024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 85
Canonical embedding of rectangular duals with applications to VLSI floorplanning 矩形对偶的规范嵌入及其在VLSI平面规划中的应用
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227859
S. Sur-Kolay, B. Bhattacharya
{"title":"Canonical embedding of rectangular duals with applications to VLSI floorplanning","authors":"S. Sur-Kolay, B. Bhattacharya","doi":"10.1109/DAC.1992.227859","DOIUrl":"https://doi.org/10.1109/DAC.1992.227859","url":null,"abstract":"The notion of equivalent embedding of rectangular duals is introduced, leading to a new concept of canonical embedding of a rectangular dual; this is a floorplan corresponding to a given neighborhood graph such that the number of directed cycles in its channel digraph is minimum. Strongly maximal rectangular hierarchy (sMRH) in nonslicible floorplans is then defined. The canonical form of any arbitrary floorplan consists of at most one nonslicing core for each member of sMRH. Such an embedding therefore represents a floorplan with minimum deviations from a slicing structure. An O(n/sup 2/) algorithm for realizing a canonical embedding is also presented. Canonical embedding lends deep insight to the yet unsolved problem of characterizing inherent nonslicibility and motivates design for slicibility. It also makes determination of safe routing order simple.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126830649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A boundary-element approach to transient simulation of three-dimensional integrated circuit interconnect 三维集成电路互连瞬态仿真的边界元方法
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227855
D. D. Ling, S. Kim, Jacob K. White
{"title":"A boundary-element approach to transient simulation of three-dimensional integrated circuit interconnect","authors":"D. D. Ling, S. Kim, Jacob K. White","doi":"10.1109/DAC.1992.227855","DOIUrl":"https://doi.org/10.1109/DAC.1992.227855","url":null,"abstract":"The authors demonstrate that boundary-element techniques can be used to perform very efficient transient simulation of three-dimensional interconnect structures, fast enough to easily be included in a circuit simulator. Two boundary element approaches are investigated, and it is shown that the most straight-forward approach leads to unacceptable discretization errors and a less intuitive second approach yields good results even with coarse surface meshes. Results of numerical experiments demonstrating the effectiveness of the second approach in calculating cross-talk are presented.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126759982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A wire length estimation technique utilizing neighborhood density equations 利用邻域密度方程的导线长度估计技术
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227861
T. Hamada, Chung-Kuan Cheng, P. Chau
{"title":"A wire length estimation technique utilizing neighborhood density equations","authors":"T. Hamada, Chung-Kuan Cheng, P. Chau","doi":"10.1109/DAC.1992.227861","DOIUrl":"https://doi.org/10.1109/DAC.1992.227861","url":null,"abstract":"A new wire length estimation technique is presented. Wire length distribution is modeled by wire density on a 2-D lattice. Assuming a pointwise independent branching process, the wire length distribution is found by solving the neighborhood density equations. For several industrial circuits tested, this technique achieved an estimation error of 9.0% with a maximum deviation of +16.3%, which compared favorably with other techniques recently proposed.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117156686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 47
On the over-specification problem in sequential ATPG algorithms 序列ATPG算法中的超规范问题
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227870
K. Cheng, H. Ma
{"title":"On the over-specification problem in sequential ATPG algorithms","authors":"K. Cheng, H. Ma","doi":"10.1109/DAC.1992.227870","DOIUrl":"https://doi.org/10.1109/DAC.1992.227870","url":null,"abstract":"The authors show that some ATPG (automatic test pattern generation) programs may err in identifying untestable faults. These test generators may not be able to find the test sequence for a testable fault, even allowed infinite run time, and may mistakenly claim it as untestable. The main problem of these programs is that the underlying combinational test generation algorithm may over-specify the requirements at the present state lines. A necessary condition that the underlying combinational test generation algorithm must satisfy is considered to ensure a correct sequential ATPG program. It is shown that the simple D-algorithm satisfies this condition while PODEM and the enhanced D-algorithm do not. The impact of over-specification on the length of the generated test sequence was studied. Over-specification caused a longer test sequence. Experimental results are presented.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128973034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Exact calculation of synchronization sequences based on binary decision diagrams 基于二元决策图的同步序列精确计算
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227811
C. Pixley, Seh-Woong Jeong, G. Hachtel
{"title":"Exact calculation of synchronization sequences based on binary decision diagrams","authors":"C. Pixley, Seh-Woong Jeong, G. Hachtel","doi":"10.1109/DAC.1992.227811","DOIUrl":"https://doi.org/10.1109/DAC.1992.227811","url":null,"abstract":"A synchronization sequence for a synchronous design D is a sequence of primary input vectors which when applied to any initial state of D will drive D to a single state, called a reset state. The authors present efficient methods based upon the universal alignment theorem and binary decision diagrams to compute a synchronization sequence, to compute a tight lower bound for the length of such a sequence, and to check that an initial state given in the specification is a reset state. It was shown in the experiments that the proposed method can handle fairly large circuits and the length of the actual synchronization sequence computed is quite close to the lower bound.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130238933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 58
Maximum current estimation in CMOS circuits CMOS电路中的最大电流估计
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227873
H. Kriplani, F. Najm, I. Hajj
{"title":"Maximum current estimation in CMOS circuits","authors":"H. Kriplani, F. Najm, I. Hajj","doi":"10.1109/DAC.1992.227873","DOIUrl":"https://doi.org/10.1109/DAC.1992.227873","url":null,"abstract":"The authors propose pattern-independent, linear-time algorithms that provide tight upper bounds on maximum envelope current (MEC) waveforms. The proposed approach represents a trade-off between execution speed and tightness of these bounds. The MEC waveform is a point-wise maximum on all the possible waveforms that the circuit can draw. Experimental results on several benchmark circuits are provided to establish the usefulness of this approach.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127901535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 68
Optimal allocation and binding in high-level synthesis 高级合成中的优化配置与结合
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227850
Minjoong Rim, R. Jain, R. Leone
{"title":"Optimal allocation and binding in high-level synthesis","authors":"Minjoong Rim, R. Jain, R. Leone","doi":"10.1109/DAC.1992.227850","DOIUrl":"https://doi.org/10.1109/DAC.1992.227850","url":null,"abstract":"The authors present an integer linear program (ILP) formulation for the allocation and binding problem in high-level synthesis. Given a behavioral specification and a time-step schedule of operations, the formulation minimizes wiring and multiplexer areas. An ILP model for minimizing multiplexer and wiring areas has been mathematically formulated and optimally solved. The model handles chaining, multi-cycle operations, pipelined modules, conditional branches and trades off wiring area with resource area.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"452 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115959098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 47
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