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[1992] Proceedings 29th ACM/IEEE Design Automation Conference最新文献

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Multipole-accelerated 3-D capacitance extraction algorithms for structures with conformal dielectrics 保形介质结构的多极加速三维电容提取算法
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227794
K. Nabors, Jacob K. White
{"title":"Multipole-accelerated 3-D capacitance extraction algorithms for structures with conformal dielectrics","authors":"K. Nabors, Jacob K. White","doi":"10.1109/DAC.1992.227794","DOIUrl":"https://doi.org/10.1109/DAC.1992.227794","url":null,"abstract":"The new three-dimensional capacitance calculation program FASTCAP2 is described. Like the earlier program FASTCAP, FASTCAP2 is based on a multipole-accelerated algorithm that is efficient enough to allow three-dimensional capacitance calculations to be part of an iterative design process. FASTCAP2 differs from FASTCAP in that it was able to analyze problems with multiple-dielectrics, thus extending the applicability of the multiple-accelerated approach to a wider class of integrated circuit interconnect and packaging problems.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"236 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121982612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Two new techniques for compiled multi-delay logic simulation 编译多延迟逻辑仿真的两种新技术
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227767
Y. Lee, P. Maurer
{"title":"Two new techniques for compiled multi-delay logic simulation","authors":"Y. Lee, P. Maurer","doi":"10.1109/DAC.1992.227767","DOIUrl":"https://doi.org/10.1109/DAC.1992.227767","url":null,"abstract":"The authors describe two techniques for compiled event driven multidelay logic simulation that provide significant performance improvements over interpreted multidelay logic simulation. These two techniques are based on the concept of retargetable branch instructions that can be used to switch segments of code into and out of the instruction stream. The second algorithm, called the shadow technique, has been designed especially for systems with instruction caches. Benchmark experiments showed that these two techniques were up to 15 times faster than the interpreted multidelay simulator, with an average improvement of about five times for the fastest method.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114601944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Power and ground network topology optimization for cell based VLSIs 基于小区的vlsi的电源和接地网络拓扑优化
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227748
T. Mitsuhashi, E. Kuh
{"title":"Power and ground network topology optimization for cell based VLSIs","authors":"T. Mitsuhashi, E. Kuh","doi":"10.1109/DAC.1992.227748","DOIUrl":"https://doi.org/10.1109/DAC.1992.227748","url":null,"abstract":"A new power and ground network design problem for cell-based VLSIs is discussed. In contrast to the conventional method, the network topology is optimized, or wiring resource consumption subject to electromigration and voltage drop constraints is minimized. The proposed method has been implemented. Using several examples, the validity of the problem formulation and the solution method was confirmed. Experimental results showed that brute power bus enhancement was meaningless and smart power and ground topologies significantly reduced the consumption of wiring resources.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130022182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 84
LATTIS: an iterative speedup heuristic for mapped logic 映射逻辑的迭代加速启发式算法
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227754
J. Fishburn
{"title":"LATTIS: an iterative speedup heuristic for mapped logic","authors":"J. Fishburn","doi":"10.1109/DAC.1992.227754","DOIUrl":"https://doi.org/10.1109/DAC.1992.227754","url":null,"abstract":"The author describes heuristic problems for performance optimization of mapped combinational logic, implemented in the system LATTIS (logic area-time tradeoff for integrated systems). LATTIS currently has six transform types: gate repowering, buffer insertion, downpowering of noncritical fanouts of the critical path, gate duplication, DeMorgan's laws, and timing-directed factorization and remapping of subcircuits. From among the transforms applicable on the critical path. LATTIS chooses the one with maximum benefit/cost. Cost is increase in area, and benefit is improvement in local slack, weighted by the number of primary input/outputs affected. The delay-area curves produced by LATTIS for the 70 largest circuits of the 1991 MCNC multilevel combinational logic benchmark set are given.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117127234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
Implicit and incremental computation of primes and essential primes of Boolean functions 布尔函数的素数和本质素数的隐式和增量计算
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227866
O. Coudert, J. Madre
{"title":"Implicit and incremental computation of primes and essential primes of Boolean functions","authors":"O. Coudert, J. Madre","doi":"10.1109/DAC.1992.227866","DOIUrl":"https://doi.org/10.1109/DAC.1992.227866","url":null,"abstract":"Recently introduced implicit set manipulation techniques have made it possible to formally verify finite state machines with state graphs too large to be built. The authors show that these techniques can also be used with success to compute and manipulate implicitly large sets of prime and of essential prime implicants of incompletely specified Boolean functions. These sets are denoted by meta-products that are represented with binary decision diagrams (BDDs). Two procedures are described. The first is based on the standard BDD operators, and the second, more efficient, takes advantage of the structural properties of BDDs and of meta-products to handle a larger class of functions than the first procedure.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123341457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 179
Concurrent fault simulation of logic gates and memory blocks on message passing multicomputers 消息传递多机逻辑门和存储块并发故障仿真
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227783
S. Bose, P. Agrawal
{"title":"Concurrent fault simulation of logic gates and memory blocks on message passing multicomputers","authors":"S. Bose, P. Agrawal","doi":"10.1109/DAC.1992.227783","DOIUrl":"https://doi.org/10.1109/DAC.1992.227783","url":null,"abstract":"The authors present a concurrent fault simulation algorithm. The pipelined algorithm is suitable for implementation on memory limited hardware accelerators and message passing multicomputers or specialized hardware. The architecture of the system and the data structures and algorithms for some of the crucial parts of the fault simulation algorithm are outlined. For pipelined architectures, fault simulation is illustrated for circuits modeled at mixed functional and gate levels. The results indicate an order of magnitude speed up compared to a production quality simulator running on a SUN SPARC2.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115167576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Incremental circuit simulation using waveform relaxation 增量电路仿真使用波形松弛
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227872
Yun-Cheng Ju, R. Saleh
{"title":"Incremental circuit simulation using waveform relaxation","authors":"Yun-Cheng Ju, R. Saleh","doi":"10.1109/DAC.1992.227872","DOIUrl":"https://doi.org/10.1109/DAC.1992.227872","url":null,"abstract":"Two algorithms were developed using waveform relaxation for the rapid re-simulation of circuits that have been modified slightly compared to a previous simulation run. Both local and global changes can be handled so long as the changes are relatively small. In this approach, the window sizes, step sizes, and final waveforms from a previous simulation were used to drive the incremental simulation. In addition, a selective storage scheme was used to reduce the overhead associated with saving the waveforms from a previous run. Experimental results indicated that the run-time using the incremental approach can be reduced by an order of magnitude compared to a complete re-simulation.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124121660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A mixed-integer nonlinear programming approach to analog circuit synthesis 模拟电路合成的混合整数非线性规划方法
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227796
P. C. Maulik, L. Carley, Rob A. Rutenbar
{"title":"A mixed-integer nonlinear programming approach to analog circuit synthesis","authors":"P. C. Maulik, L. Carley, Rob A. Rutenbar","doi":"10.1109/DAC.1992.227796","DOIUrl":"https://doi.org/10.1109/DAC.1992.227796","url":null,"abstract":"A mixed-integer nonlinear programming (MINLP) approach to cell-level analog circuit synthesis, allowing simultaneous topology selection and parameter selection, is presented. The problem formulation uses integer variables to model topology choices and continuous variables for the design parameters such as device sizes and bias voltages. Examples using a branch and bound approach to efficiently solve the MINLP problem for CMOS two-stage operational amplifiers are given.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134040864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
FREEZE: a new approach for testing sequential circuits 冻结:一种测试顺序电路的新方法
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227869
M. Abramovici, K. Rajan, David T. Miller
{"title":"FREEZE: a new approach for testing sequential circuits","authors":"M. Abramovici, K. Rajan, David T. Miller","doi":"10.1109/DAC.1992.227869","DOIUrl":"https://doi.org/10.1109/DAC.1992.227869","url":null,"abstract":"The authors present a new approach for testing sequential circuits which extends the classical concept of a test sequence. The classical approach applies only one vector in every state. In contrast, the new approach temporarily disables the sequential behavior of the circuit by holding the clock inactive and applies a group of vectors in every state. In this way many faults can be combinationally detected. A test generation algorithm called FIRST (fault-independent rapid sequential test generator) was developed based on the new approach. FIRST detected a large percentage of the faults that were detected by a conventional fault-oriented sequential test generator in less CPU time and with shorter sequences.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"430 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132243874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
An approach to symbolic timing verification 符号时序验证的一种方法
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227769
T. Amon, G. Borriello
{"title":"An approach to symbolic timing verification","authors":"T. Amon, G. Borriello","doi":"10.1109/DAC.1992.227769","DOIUrl":"https://doi.org/10.1109/DAC.1992.227769","url":null,"abstract":"Symbolic timing verification is a critical tool in the development of higher-level synthesis tools. The authors present an approach to symbolic timing verification using constraint logic programming techniques. The techniques are quite powerful in that they not only yield simple bounds on delays but also relate the delays in linear inequalities so that tradeoffs are apparent. They model circuits as communicating processes and the current implementation can verify a large class of mixed synchronous and asynchronous specifications. The utility of the approach is illustrated with some examples.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127583601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
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