发布求助
文献互助 智能选刊 最新文献

[1992] Proceedings 29th ACM/IEEE Design Automation Conference最新文献

筛选
英文 中文
Generalized moment-matching methods for transient analysis of interconnect networks 互联网络暂态分析的广义矩匹配方法
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227836
E. Chiprout, M. Nakhla
{"title":"Generalized moment-matching methods for transient analysis of interconnect networks","authors":"E. Chiprout, M. Nakhla","doi":"10.1109/DAC.1992.227836","DOIUrl":"https://doi.org/10.1109/DAC.1992.227836","url":null,"abstract":"An approach is introduced which improves published moment matching methods used in transient waveform estimation of large linear networks including lossy, coupled transmission lines. The method, which selects from a general set of moment-matching approximations, ensures stability while increasing the accuracy of the transient response. The technique is useful for analysis of high-speed interconnects including lumped and distributed linear components with nonlinear terminations. Examples are presented which demonstrate the stability and accuracy of the new method.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114976430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 47
A graph theoretic technique to speed up floorplan area optimization 一种加速平面面积优化的图论技术
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227860
Ting-Chi Wang, D. F. Wong
{"title":"A graph theoretic technique to speed up floorplan area optimization","authors":"Ting-Chi Wang, D. F. Wong","doi":"10.1109/DAC.1992.227860","DOIUrl":"https://doi.org/10.1109/DAC.1992.227860","url":null,"abstract":"The authors present two algorithms to optimally select implementations for rectangular and L-shaped subfloorplans. The algorithms are designed specifically for the floorplan optimization algorithm given by T.-C. Wang and D.F. Wong (see Proc. 27th ACM/IEEE Des. Autom. Conf., p.180-6 (1990)), but they can also be applied to other algorithms as well. The experimental results, based on incorporating the two algorithms into Wang's algorithm, whose performance was considerably improved were very encouraging. For the test runs where Wang's algorithm failed to run, the algorithms helped to produce satisfactory solutions.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114611953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Net partitions yield better module partitions Net分区产生更好的模块分区
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227863
J. Cong, L. Hagen, A. Kahng
{"title":"Net partitions yield better module partitions","authors":"J. Cong, L. Hagen, A. Kahng","doi":"10.1109/DAC.1992.227863","DOIUrl":"https://doi.org/10.1109/DAC.1992.227863","url":null,"abstract":"The authors demonstrate that the dual intersection graph of the netlist strongly captures circuit properties relevant to partitioning. The main contribution of the analysis highlights advantages to using the dual representation of the logic design, and confirming that net structure and interrelationships, rather than module adjacencies, should constitute the primary descriptors of a circuit. In particular, the dual intersection graph representation of the netlist hypergraph yields much more natural circuit partitioning formulations, since it inherently emphasizes relationships between signal nets. The intersection graph yields a sparser circuit representation than traditional net models. An efficient algorithm, called IG-Match, is proposed for completing the net partition. The IG-Match method yielded significant performance improvements over previous ratio-cut partitioning methods.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122034458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 61
Hcompare: a hierarchical netlist comparison program Hcompare:一个分层网表比较程序
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227789
Pradeep Batra, David Cooke
{"title":"Hcompare: a hierarchical netlist comparison program","authors":"Pradeep Batra, David Cooke","doi":"10.1109/DAC.1992.227789","DOIUrl":"https://doi.org/10.1109/DAC.1992.227789","url":null,"abstract":"The authors present Hcompare, a hierarchical comparison tool. This tool does a true hierarchical comparison with the user-defined hierarchies. Errors are reported hierarchically in terms of user-defined blocks. Error reports are easy to read as errors are reported in terms of mismatched connections to design blocks. Run time is on the order of minutes even for large blocks with 2-3 million devices. Input to the tool is in the form of two netlists: one from the definition, typically schematic, and one from implementation, typically layout. The program has been used to compare layout vs schematic netlists for two chips with over two million devices each.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129274247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Routing considerations in symbolic layout synthesis 符号布局合成中的路由考虑
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227799
Youlin Liao, S. Chow
{"title":"Routing considerations in symbolic layout synthesis","authors":"Youlin Liao, S. Chow","doi":"10.1109/DAC.1992.227799","DOIUrl":"https://doi.org/10.1109/DAC.1992.227799","url":null,"abstract":"The authors discuss routing styles, including a newly proposed hybrid routing style, in basic silicon-level design for a symbolic layout synthesis tool with practical considerations for design rules and process technology. Methods for systematically adding jogs in the layout to achieve high layout quality are proposed. Algorithms for input/output-pin assignment and for pin-ordering routing that achieve a minimal number of vias are also presented. Experiments on real industry designs showed promising results.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124649686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Data path allocation using an extended binding model 使用扩展绑定模型分配数据路径
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227792
Ganesh Krishnamoorthy, J. Nestor
{"title":"Data path allocation using an extended binding model","authors":"Ganesh Krishnamoorthy, J. Nestor","doi":"10.1109/DAC.1992.227792","DOIUrl":"https://doi.org/10.1109/DAC.1992.227792","url":null,"abstract":"Existing approaches to data path allocation in high-level synthesis use a binding model in which values are assigned to the same register for their entire lifetimes. The authors describe an extended binding model in which segments of a value's lifetime may reside in different registers if there is a cost advantage in doing so. In addition, the model supports multiple copies of values and the use of functional units to pass through unmodified values to reduce interconnects. This model was exploited in an allocation tool that used iterative improvement to search for low-cost designs. Results showed that allocation costs can be substantially reduced by using this model.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129988447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 49
Partitioning by regularity extraction 正则抽取分区
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.5555/113938.149419
D. S. Rao, F. Kurdahi
{"title":"Partitioning by regularity extraction","authors":"D. S. Rao, F. Kurdahi","doi":"10.5555/113938.149419","DOIUrl":"https://doi.org/10.5555/113938.149419","url":null,"abstract":"The authors present a general methodology for extracting regularity at any level of hierarchy, and explore the problem of digital system partitioning by extraction of regularity. They consider system-level partitioning to demonstrate that regularity can lead to reduced design costs. The digital system is modeled with cyclic directed graphs. A prototype system based on these ideas has been built. Some examples are discussed.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134338337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 67
Global scheduling independent of control dependencies based on condition vectors 基于条件向量的不依赖于控制的全局调度
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227852
K. Wakabayashi, Hirohito Tanaka
{"title":"Global scheduling independent of control dependencies based on condition vectors","authors":"K. Wakabayashi, Hirohito Tanaka","doi":"10.1109/DAC.1992.227852","DOIUrl":"https://doi.org/10.1109/DAC.1992.227852","url":null,"abstract":"The authors present a global scheduling method based on condition vectors. The proposed method exploits global parallelism. The technique can schedule operations independent of control dependencies. It transforms the control structure of the given behavior drastically, while preserving semantics to minimize the number of states in final schedule. The method can parallelize multiple nests of conditional branches and optimize across the boundaries of basic blocks. It can also optimize all possible execution paths. An algorithm is proposed which generates a single finite state machine controller from parallel individual control sequences derived in the global parallelization process. Experimental results prove that the global parallelization is very effective.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132797443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 147
Automatic test knowledge extraction from VHDL (ATKET) 基于VHDL的测试知识自动提取(ATKET)
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227793
P. Vishakantaiah, J. Abraham, M. Abadir
{"title":"Automatic test knowledge extraction from VHDL (ATKET)","authors":"P. Vishakantaiah, J. Abraham, M. Abadir","doi":"10.1109/DAC.1992.227793","DOIUrl":"https://doi.org/10.1109/DAC.1992.227793","url":null,"abstract":"The authors describe ATKET (automatic test knowledge extraction tool), which synthesizes test knowledge using structural and behavioral information available in the very high-speed IC description language (VHDL) description of a design. A VHDL analyzer produces an intermediate representation of the information contained in a VHDL design. ATKET interfaces to this intermediate representation to access structural and behavioral information in the design and stores it in suitable data structures. A convenient representation called the module operation tree (MOT) is used to capture the behavior of modules in the design. Information stored in the MOT along with structural information describing connections between modules in the design is used to generate test knowledge. Results obtained from ATKET for a circuit which was difficult to test are presented.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133122543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 69
ISIS: a system for performance driven resource sharing ISIS:一个性能驱动的资源共享系统
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227791
Brent Gregory, D. MacMillen, Dennis C. Fogg
{"title":"ISIS: a system for performance driven resource sharing","authors":"Brent Gregory, D. MacMillen, Dennis C. Fogg","doi":"10.1109/DAC.1992.227791","DOIUrl":"https://doi.org/10.1109/DAC.1992.227791","url":null,"abstract":"The authors establish the importance of accurate bit-level area and delay modeling to the quality of circuits synthesized by resource sharing systems. They show that bit-level accuracy and integration with logic optimization are both desirable and feasible, since the added execution time is a small fraction of the total optimization time. The implementation of a resource sharing system called ISIS, which uses bit-level modeling, accounts for control delays, and optimizes sharing and resource performance selection together to generate high-quality circuits from register transfer language (RTL) descriptions, is described.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123984379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信